Shielded gate field effect transistor with improved inter-poly dielectric

• US 7,385,248 B2
• Filed: 08/09/2005
• Issued: 06/10/2008
• Est. Priority Date: 08/09/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Herrick, Robert, Probst, Dean, Session, Fred
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US11/201,400
• Publication Number:
  US 20070037327A1
• Time in Patent Office: 1,036 Days
• Field of Search: 257/139, 257/203, 257/213, 257/678, 257/330, 257/332, 257/E29.2, 257/E29.201, 438/151, 438/253, 438/270, 438/275, 438/315
• US Class Current: 257/330
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A field effect transistor (FET) includes a trench extending into a silicon region of a first conductive type. A shield insulated from the silicon region by a shield dielectric extends in a lower portion of the trench. A gate electrode is in the trench over but insulated from the shield electrode by an inter-poly dielectric (IPD). The IPD comprises a conformal layer of dielectric and a thermal oxide layer.

Claims

1. A field effect transistor (FET) comprising:

a trench extending into a silicon region of a first conductivity type;

a shield electrode in a lower portion of the trench, the shield electrode being insulated from the silicon region by a shield dielectric; and

a gate electrode in the trench over but insulated from the shield electrode by an inter-poly dielectric (IPD), the IPD comprising a conformal layer of dielectric and a thermal oxide layer.

2. The FET of claim 1 wherein the gate electrode is insulated from the silicon region by a gate dielectric extending along upper trench sidewalls, and a ratio of a thickness of the IPD to a thickness of the gate dielectric is greater than three to one.

3. The FET of claim 1 wherein the IPD has a concave profile along its upper surface.

4. The FET of claim 1 wherein the gate electrode has a concave profile along its lower surface.

5. The FET of claim 1 wherein the conformal layer of dielectric is surrounded by the thermal dielectric along its lower surface and sidewalls.

6. The FET of claim 1 wherein the conformal layer of dielectric has a convex lower surface and a concave upper surface.

7. The FET of claim 1 wherein the shield electrode has a rounded top surface.

8. The FET of claim 1 wherein the silicon region comprises:

an epitaxial layer of the first conductivity type extending over a substrate of the first conductivity type;

well regions of a second conductivity type in the epitaxial layer; and

source regions of the first conductivity in the well regions, the source regions flanking the trench.

9. The FET of claim 8 wherein the trench extends into and terminates within the epitaxial layer.

10. The FET of claim 8 wherein the trench extends through the epitaxial layer and terminates within the substrate.

11. A field effect transistor (FET) comprising:

a trench extending into a silicon region of a first conductivity type;

a shield electrode in a lower portion of the trench, the shield electrode being insulated from the silicon region by a shield dielectric; and

a gate electrode in the trench over but insulated from the shield electrode by an inter-poly dielectric (IPD) having a concave profile along at least a center portion of its upper surface.

12. The FET of claim 11 wherein the shield electrode has a rounded top surface.

13. The FET of claim 11 wherein the silicon region comprises:

an epitaxial layer of the first conductivity type extending over a substrate of the first conductivity type;

well regions of a second conductivity type in the epitaxial layer; and

source regions of the first conductivity in the well regions, the source regions flanking the trench.

14. The FET of claim 13 wherein the trench extends into and terminates within the epitaxial layer.

15. The FET of claim 13 wherein the trench extends through the epitaxial layer and terminates within the substrate.

16. A field effect transistor (FET) comprising:

a trench extending into a silicon region of a first conductivity type;

a shield electrode in a lower portion of the trench, the shield electrode being insulated from the silicon region by a shield dielectric; and

a gate electrode in the trench over but insulated from the shield electrode by an inter-poly dielectric (IPD), the IPD comprising a conformal layer of dielectric which has a convex profile along its lower surface and a concave profile along its upper surface.

17. The FET of claim 16 wherein the gate electrode has a concave profile along its lower surface.

18. The FET of claim 16 wherein the IPD further comprises a thermal dielectric surrounding the conformal layer of dielectric along its lower surface and sidewalls.

19. The FET of claim 16 wherein the silicon region comprises:

an epitaxial layer of the first conductivity type extending over a substrate of the first conductivity type;

well regions of a second conductivity type in the epitaxial layer; and

source regions of the first conductivity in the well regions, the source regions flanking the trench.

20. The FET of claim 19 wherein the trench extends into and terminates within the epitaxial layer.

21. The FET of claim 19 wherein the trench extends through the epitaxial layer and terminates within the substrate.