Semiconductor device having silicide thin film and method of forming the same

• US 7,385,260 B2
• Filed: 04/21/2004
• Issued: 06/10/2008
• Est. Priority Date: 03/19/2001
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwon, Hyung-Shin, Joo, Joon-Yong, Kim, Sung-Bong, Koh, Kwang-Ok
• Primary Examiner(s): Pham; Long
• Application Number:
  US10/830,390
• Publication Number:
  US 20040198032A1
• Time in Patent Office: 1,511 Days
• Field of Search: 257/383, 257/384, 257/770
• US Class Current: 257/383
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66507 providing different silicide thicknesses on the gate and on source or drain
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 Å in the impurity region.

Claims

1. A semiconductor device, comprising:

a gate insulation layer on an active region of a semiconductor substrate;

a gate electrode on the gate insulation layer;

a lightly-doped source/drain region at both sides of the gate electrode in the active region;

a first spacer on sidewalls of the gate electrode and on at least a portion of the lightly-doped source/drain regions, wherein the first spacer is L-shaped and comprises silicon oxide;

a second spacer on the first spacer, wherein the second spacer comprises silicon nitride;

a heavily-doped source/drain region at both sides of the gate electrode and adjacent to the second spacer;

a cobalt silicide layer on the heavily-doped source/drain regions; and

a subsidiary layer covering the cobalt silicide layer, the first spacer and the second spacer, wherein the subsidiary layer has a higher oxygen concentration in a lower portion of the subsidiary layer contacting the cobalt silicide layer than in another portion of the subsidiary layer not contacting the cobalt silicide layer.

2. The semiconductor device of claim 1, wherein the subsidiary layer comprises silicon oxynitride.

3. The semiconductor device of claim 1, further comprising an interlayer insulating layer disposed on the subsidiary layer.

4. The semiconductor device of claim 1, whereinfurther comprising a metal silicide layer on top of the gate electrode.

5. The semiconductor device of claim 4, wherein the metal silicide layer is thicker than the cobalt silicide layer.

6. The semiconductor device of claim 4, wherein the metal suicide layer does not contact the second spacer.

7. The semiconductor device of claim 1, wherein an uppermost surface of the cobalt silicide layer is disposed at a height lower than a bottom surface of the second spacer.

8. A semiconductor device, comprising:

a gate insulation layer formed on a semiconductor substrate;

a gate electrode formed on the gate insulation layer;

source/drain regions formed in the semiconductor substrate, wherein the source/drain regions comprise a lightly-doped region and a heavily-doped region;

a spacer formed on sidewalls of the gate electrode, wherein the spacer comprises an inner spacer and an outer spacer, wherein the inner spacer is adjacent to the gate electrode and comprises silicon oxide, wherein the outer spacer comprises silicon nitride and wherein the inner spacer has an L-shape;

a cobalt silicide layer formed on the source/drain regions;

a silicon oxynitride layer covering the cobalt suicide layer, the inner spacer and the outer spacer; and

a metal silicide layer on top of the gate electrode, wherein the metal silicide layer does not contact the outer spacer.

9. The semiconductor device of claim 8, wherein a portion of the silicon oxynitride layer has a higher oxygen concentration in a portion contacting the cobalt suicide layer in comparison to a portion not contacting the cobalt suicide layer.

10. The semiconductor device of claim 8, wherein the metal silicide layer is thicker than the cobalt silicide layer.

11. The semiconductor device of claim 8, wherein an uppermost surface of the cobalt suicide layer is disposed at a height lower than a bottom surface of the outer spacer.

12. A semiconductor device, comprising:

a gate insulation layer on an active region of a semiconductor substrate;

a gate electrode on the gate insulation layer;

source/drain regions within the active region, each of the regions extending outwardly from each side of the gate electrode, the source/drain regions each comprising a lightly doped region and a heavily doped region;

a first spacer on both sides of the gate electrode and on at least a portion of the lightly doped region of the source/drain regions, wherein the first spacer is L-shaped;

a second spacer being disposed on the first spacer;

a cobalt silicide layer located on top of at least a portion of the heavily doped region of the source/drain regions, an uppermost surface of the cobalt silicide layer being disposed at a height lower than a bottom surface of the second spacer; and

a subsidiary layer covering the cobalt silicide layer and the second spacer, wherein a portion of the subsidiary layer facing the cobalt silicide layer has a higher oxygen concentration than a portion of the subsidiary layer facing away from the cobalt suicide layer.

13. The semiconductor device of claim 12, further comprising a metal silicide layer on top of the gate electrode.

14. The semiconductor device of claim 13, wherein the metal silicide layer is thicker than the cobalt silicide layer.

15. The semiconductor device of claim 13, wherein the metal silicide layer does not contact the second spacer.