Semiconductor module

• US 7,385,286 B2
• Filed: 06/05/2002
• Issued: 06/10/2008
• Est. Priority Date: 06/05/2001
• Status: Expired due to Term

• Current Assignee: III Holdings 12, LLC (Intellectual Ventures LLC)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Taguchi, Yutaka, Ogura, Tetsuyoshi, Iwaki, Hideki
• Primary Examiner(s): THAI, LUAN C
• Application Number:
  US10/161,719
• Publication Number:
  US 20020180063A1
• Time in Patent Office: 2,197 Days
• Field of Search: 257/724, 257/698, 257/532, 257/691, 257/692, 257/E23.062, 361/763, 361/306.3, 361/306.2
• US Class Current: 257/724
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01025 Manganese [Mn]
• CPC Class Codes: H01L 2924/01037 Rubidium [Rb]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0306 : Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/162 : incorporating printed capacitors
• CPC Class Codes: H05K 1/165 : incorporating printed inductors
• CPC Class Codes: H05K 1/167 : incorporating printed resistors
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/09763 : Printed component having superposed conductors, but integrated in one circuit layer
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 3/4614 : the electrical connections between the circuit boards being made during lamination
• CPC Class Codes: H05K 3/4617 : characterized by laminating only or mainly similar single-sided circuit boards
• CPC Class Codes: H05K 3/462 : characterized by laminating only or mainly similar double-sided circuit boards
• CPC Class Codes: H05K 3/4629 : laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Abstract

At least four terminal electrodes are provided on a surface of multi-layer substrate main body. An electric functional layer is selectively provided at an internal area of said multi-layer substrate placed at a downward position of all terminal electrodes in a substrate thickness direction. A semiconductor device is flip-chip-bonded to the terminal electrodes. Thus, the semiconductor device is electrically connected to the electric functional layer at a short distance. As a result, a reduction in parasitic inductance and an improvement in high frequency characteristic can be accomplished. Generation of height variations between the terminal electrodes can be prevented, and the semiconductor device is stably flip-chip-bonded to the multi-layer substrate.

Claims

1. A semiconductor module comprising:

a multi-layer substrate;

at least four terminal electrodes provided on a surface of said multi-layer substrate;

a capacitive element layer which is selectively provided at an internal area of said multi-layer substrate placed directly below all of said terminal electrodes in a substrate thickness direction, said capacitive element layer is encapsulated by a different material comprising the multi-layer substrate; and

a semiconductor device which is flip-chip-bonded to said terminal electrodes,

wherein the height variation of said terminal electrodes provided on the surface of said multi-layer substrate is equal to or less than 10 μ

m;

internal electrodes are provided on opposite sides of said capacitive element layer in the substrate thickness direction; and

longitudinal length of said internal electrodes is smaller than a length equivalent to a quarter-wavelength of a wavelength of an electronic signal inputted into said semiconductor device.

2. The semiconductor module according to claim 1, wherein said capacitive element layer is one of a dielectric layer, a resistor layer and a magnetic material layer.

3. The semiconductor module according to claim 2, wherein said semiconductor device is flip-chip bonded to said terminal electrodes by use of a conductive adhesive.

4. The semiconductor module according to claim 1 comprising a conductive material which is provided at the internal area of said multi-layer substrate placed at a downward position of said terminal electrodes in the substrate thickness direction and which electrically connects said capacitive element layer and said terminal electrodes.

5. The semiconductor module according to claim 4, wherein said semiconductor device is flip-chip bonded to said terminal electrodes by use of a conductive adhesive.

6. The semiconductor module according to claim 1, wherein an area that said capacitive element layer is not present is provided at the internal area of said multi-layer substrate placed below a central portion of said semiconductor device in the substrate thickness direction.

7. The semiconductor module according to claim 1, wherein said terminal electrodes are provided on the opposite surfaces of said multi-layer substrate, and said semiconductor device is flip-chip-bonded to the terminal electrodes on the opposite surfaces of substrate.

8. The semiconductor module according to claim 1, wherein an internal electrode is provided at the opposite surfaces of said capacitive element layer in the substrate thickness direction, and a longitudinal direction of said internal electrode is set so as to be smaller than a dimension corresponding to a ¼

wavelength of wavelength of electric signal to be inputted to said semiconductor device.

9. The semiconductor module according to claim 8, wherein a longitudinal direction of said internal electrode is set so as to be smaller than a dimension corresponding to a ⅛

wavelength of wavelength of electric signal to be inputted to said semiconductor device.

10. The semiconductor module according to claim 1, wherein the internal electrode is provided at the opposite surfaces of said capacitive element layer in the substrate thickness direction, and the internal electrode is divided into a plurality of parts.

11. The semiconductor module according to claim 10, wherein said internal electrode is divided into a plurality of parts along the area that said terminal electrode is not formed.

12. The semiconductor module according to claim 1, wherein said capacitive element layer is provided on a surface portion of said multi-layer substrate.

13. The semiconductor module according to claim 1, wherein at least two of the dielectric layer, the resistor layer and the magnetic material layer are provided as said capacitive element layer at the same layer within said multi-layer substrate.

14. The semiconductor module according to claim 1, wherein at least two of the dielectric layer, the resistor layer and the magnetic material layer are provided as said capacitive element layer at different layers within said multi-layer substrate.

15. The semiconductor module according to claim 1, wherein the periphery of said semiconductor device is filled with a mixture containing an inorganic filler and a thermosetting resin composition.

16. The semiconductor module according to claim 15, wherein said inorganic filler contains at least one of alumina, AlN, silicon nitride and beryllia (BeO).

17. A semiconductor module, wherein a plurality of semiconductor modules according to claim 15 are provided, a back surface of said multi-layer substrate of one semiconductor module is laminated on a surface of said mixture of the other semiconductor module, and a conductive material for electrically connecting terminal electrodes of the respective semiconductor modules is provided within said mixture.

18. The semiconductor module according to claim 1, wherein at least one said capacitive element layer is substituted by an insulating layer having the same thickness as that of said capacitive element layer.

19. The semiconductor module according to claim 1 wherein an insulating material constituting said multi-layer substrate is a low-temperature sintered glass ceramics made mainly of a sintered body of inorganic material, and said capacitive element layer is a dielectric layer formed mainly of a lead-based perovskite compound.

20. The semiconductor module according to claim 1, wherein an insulating material constituting said multi-layer substrate is a low-temperature sintered glass ceramics made mainly of a sintered body of inorganic material, and said capacitive element layer is a resistor layer formed mainly of RuO₂.

21. The semiconductor module according to claim 1, wherein said capacitive element layer is continuous.

22. The semiconductor module according to claim 1, wherein said semiconductor device is flip-chip-bonded to said terminal electrodes by use of a conductive adhesive.

23. A semiconductor module comprising:

a multi-layer substrate;

at least four terminal electrodes provided on a surface of said multi-layer substrate;

a capacitive element layer which is provided at an internal area of said multi-layer substrate placed directly below said terminal electrodes in a substrate thickness direction, said capacitive element layer is encapsulated by a different material comprising the multi-layer substrate; and

a semiconductor device which is bonded to said terminal electrodes,

wherein the height variation of said terminal electrodes provided on the surface of said multi-layer substrate is equal to or less than 10 μ

m;

internal electrodes are provided on opposite sides of said capacitive element layer in the substrate thickness direction; and

longitudinal length of said internal electrodes is smaller than a length equivalent to a quarter-wavelength of a wavelength of an electronic signal inputted into said semiconductor device.

24. The semiconductor module according to claim 23, wherein said capacitive element layer is continuous.

25. A multi-layer substrate comprising:

a multi-layer substrate main body;

at least four terminal electrodes that are provided on a surface of said multi-layer substrate main body and electrically connected to an external electric component; and

a capacitive element layer which is selectively provided at an internal area of said multi-layer substrate placed directly below all terminal electrodes in a substrate thickness direction, said capacitive element layer is encapsulated by a different material comprising the multi-layer substrate,

wherein the height variation of said terminal electrodes provided on the surface of said multi-layer substrate is equal to or less than 10 μ

m;

internal electrodes are provided on opposite sides of said capacitive element layer in the substrate thickness direction; and

longitudinal length of said internal electrodes is smaller than a length equivalent to a quarter-wavelength of a wavelength of an electronic signal inputted into a semiconductor device.

26. The multi-layer substrate according to claim 25, wherein said capacitive element layer is one of a dielectric layer, a resistor layer and a magnetic material layer.

27. The multi-layer substrate according to claim 25 comprising a conductive material which is provided at said multi-layer substrate main body placed immediately below said terminal electrodes and electrically connects said capacitive element layer and said terminal electrodes.

28. The multi-layer substrate according to claim 25, wherein said capacitive element layer is continuous.