Top layers of metal for high performance IC's
First Claim
Patent Images
1. An integrated circuit chip comprising:
- a silicon substrate;
multiple devices in and on said silicon substrate, wherein one of said multiple devices comprises a transistor;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, and a second opening in said passivation layer exposing a second pad of said first metallization structure, wherein said first and second pads are separate from each other, and wherein said passivation layer comprises a topmost oxide layer of said integrated circuit chip and a topmost nitride layer of said integrated circuit chip, wherein said topmost nitride layer is over said topmost oxide layer; and
a second metallization structure over said passivation layer and over said first and second pads, a signal going up through said first opening, continuing over a distance in a direction of a horizontal plane of said second metallization structure, and descending from said second metallization structure down to said second pad by passing through said second opening.
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Abstract
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
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Citations
20 Claims
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1. An integrated circuit chip comprising:
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a silicon substrate; multiple devices in and on said silicon substrate, wherein one of said multiple devices comprises a transistor; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, and a second opening in said passivation layer exposing a second pad of said first metallization structure, wherein said first and second pads are separate from each other, and wherein said passivation layer comprises a topmost oxide layer of said integrated circuit chip and a topmost nitride layer of said integrated circuit chip, wherein said topmost nitride layer is over said topmost oxide layer; and a second metallization structure over said passivation layer and over said first and second pads, a signal going up through said first opening, continuing over a distance in a direction of a horizontal plane of said second metallization structure, and descending from said second metallization structure down to said second pad by passing through said second opening. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit chip comprising:
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a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, and a second opening in said passivation layer exposing a second pad of said first metallization structure, wherein said first and second pads are separated from each other; a polymer layer over said passivation layer, a third opening in said polymer layer exposing said first pad, and a fourth opening in said polymer layer exposing said second pad, wherein said polymer layer has a thickness of greater than 2 microns; and a second metallization structure over said polymer layer and over said first and second pads, a signal going up through said first and third openings, continuing over a distance in a direction of a horizontal plane of said second metallization structure, and descending from said second metallization structure down to said second pad by passing through said fourth and second openings. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification