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Top layers of metal for high performance IC's

  • US 7,385,291 B2
  • Filed: 07/27/2007
  • Issued: 06/10/2008
  • Est. Priority Date: 12/21/1998
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit chip comprising:

  • a silicon substrate;

    multiple devices in and on said silicon substrate, wherein one of said multiple devices comprises a transistor;

    a first dielectric layer over said silicon substrate;

    a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

    a second dielectric layer between said first and second metal layers;

    a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, and a second opening in said passivation layer exposing a second pad of said first metallization structure, wherein said first and second pads are separate from each other, and wherein said passivation layer comprises a topmost oxide layer of said integrated circuit chip and a topmost nitride layer of said integrated circuit chip, wherein said topmost nitride layer is over said topmost oxide layer; and

    a second metallization structure over said passivation layer and over said first and second pads, a signal going up through said first opening, continuing over a distance in a direction of a horizontal plane of said second metallization structure, and descending from said second metallization structure down to said second pad by passing through said second opening.

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