Top layers of metal for high performance IC's

• US 7,385,292 B2
• Filed: 08/27/2007
• Issued: 06/10/2008
• Est. Priority Date: 12/21/1998
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Mou-Shiung Lin
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US11/845,115
• Publication Number:
  US 20070290352A1
• Time in Patent Office: 288 Days
• Field of Search: 257750-773, 257/E23.163
• US Class Current: 257/758
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 : Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 : Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 : Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 : Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: Y10T 428/12542 : More than one such component
• CPC Class Codes: Y10T 428/12993 : Surface feature [e.g., rough, mirror]

Abstract

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Claims

1. An integrated circuit chip comprising:

a silicon substrate;

multiple devices in and on said silicon substrate, wherein one of said multiple devices comprises a transistor;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises aluminum;

a second dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer exposes first pad of said metallization structure, a second opening in said passivation layer exposes a second pad of said metallization structure, and a third opening in said passivation layer exposes a third pad of said metallization structure, wherein said first, second and third pads are separate from one another by an insulating material, and wherein said first, second and third pads are provided by a topmost metal layer under said passivation layer, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip;

a polymer layer over said passivation layer, wherein a fourth opening in said polymer layer exposes said first pad, a fifth opening in said polymer layer exposes said second pad, and a sixth opening in said polymer layer exposes said third pad, and wherein said polymer layer has a thickness between 2 micrometers and 30 micrometers and greater than those of said passivation layer, said first dielectric layer and said second dielectric layer; and

a clock distribution network over said polymer layer and over said first, second and third pads, wherein said clock distribution network comprises electroplated copper, wherein said first pad is connected to said second and third pads through said clock distribution network, and said second pad is connected to said third pad through said clock distribution network, and wherein said clock distribution network comprises a third metal layer having a thickness greater than those of said first and second metal layers.

2. The integrated circuit chip of claim 1, wherein said polymer layer comprises polyimide.

3. The integrated circuit chip of claim 1, wherein said clock distribution network further comprises nickel.

4. The integrated circuit chip of claim 1, wherein said clock distribution network further comprises tungsten.

5. The integrated circuit chip of claim 1, wherein said clock distribution network further comprises chromium.

6. The integrated circuit chip of claim 1, wherein said clock distribution network further comprises a sputtered metal.

7. An integrated circuit chip comprising:

a silicon substrate;

multiple devices in and on said silicon substrate, wherein one of said multiple devices comprises a transistor;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises aluminum;

a second dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer exposes a first pad of said metallization structure, a second opening in said passivation layer exposes a second pad of said metallization structure, and a third opening in said passivation layer exposes a third pad of said metallization structure, wherein said first, second and third pads are separate horn one another by an insulating material, wherein said first, second and third pads are provided by a topmost metal layer under said passivation layer, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip;

a polymer layer over said passivation layer, wherein said polymer layer has a thickness between 2 micrometers and 30 micrometers and greater than those of said passivation layer, said first dielectric layer and said second dielectric layer; and

a clock distribution network over said passivation layer and over said first, second and third pads, wherein said clock distribution network comprises electroplated copper, wherein said first pad is connected to said second and third pads through said clock distribution network, and said second pad is connected to said third pad through said clock distribution network, and wherein said clock distribution network comprises a third metal layer having a thickness greater than those of said first and second metal layers.

8. The integrated circuit chip of claim 7, wherein said polymer layer comprises polyimide.

9. The integrated circuit chip of claim 7, wherein said clock distribution network further comprises nickel.

10. The integrated circuit chip of claim 7, wherein said clock distribution network further comprises tungsten.

11. The integrated circuit chip of claim 7, wherein said clock distribution network further comprises chromium.

12. The integrated circuit chip of claim 7, wherein said clock distribution network further comprises a sputtered metal.

13. The integrated circuit chip of claim 7, wherein said clock distribution network further comprises an electroless metal.

14. An integrated circuit chip comprising:

a silicon substrate;

multiple devices in and on said silicon substrate wherein one of said multiple devices comprises a transistor;

a first dielectric layer over said silicon substrate;

a metallization structure over said fist dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises aluminum;

a second dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer exposes a first pad of said metallization structure, a second opening in said passivation layer exposes a second pad of said metallization structure, and a third opening in said passivation layer exposes a third pad of said metallization structure, wherein said first, second and third pads are separate from one another by an insulating material, wherein said first, second and third pads are provided by a topmost metal layer under said passivation layer, and wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer; and

a clock distribution network over said passivation layer and over said first, second and third pads, wherein said clock distribution network comprises electroplated copper, wherein said first pad is connected to said second and third pads through said clock distribution network, and said second pad is connected to said third pad through said clock distribution network, and wherein said clock distribution network comprises a third metal layer having a thickness greater than those of said first and second metal layers.

15. The integrated circuit chip of claim 14 further comprising a polymer layer over said passivation layer, wherein a fourth opening in said polymer layer exposes said first pad, a fifth opening in said polymer layer exposes said second pad, and a sixth opening in said polymer layer exposes said third pad, wherein said clock distribution network is over said polymer layer.

16. The integrated circuit chip of claim 15, wherein said polymer layer comprises polyimide.

17. The integrated circuit chip of claim 15, wherein said polymer layer comprises benzocyclobutene.

18. The integrated circuit chip of claim 15, wherein said polymer layer has a thickness between 2 and 30 micrometers.

19. The integrated circuit chip of claim 14, wherein said clock distribution network further comprises nickel.

20. The integrated circuit chip of claim 14, wherein said clock distribution network further comprises a sputtered metal.