Fully depleted silicon on insulator semiconductor devices

• US 7,385,436 B2
• Filed: 03/07/2007
• Issued: 06/10/2008
• Est. Priority Date: 07/11/2005
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kawahara, Takayuki, Itoh, Kiyoo, Tsuchiya, Ryuta
• Primary Examiner(s): Garber; Charles D.
• Assistant Examiner(s): Poos; John W
• Application Number:
  US11/714,844
• Publication Number:
  US 20070152736A1
• Time in Patent Office: 461 Days
• Field of Search: 327/365, 327/534, 327/531, 327/535, 327/597
• US Class Current: 327/534
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H03K 19/0027 in field effect transistor circuits
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits
• CPC Class Codes: H03K 19/018585 programmable

Abstract

A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.

Claims

1. A semiconductor device, comprising:

a MOS transistor having silicon-on-insulator structure, said silicon-on-insulator structure including double gates and a fully-depleted silicon-on-insulator layer, said double gates being a first gate and a second gate, said second gate being a well layer which exists under a buried oxide film, wherein,

said first gate of said MOS transistor is driven with a first pulse, said second gate of said MOS transistor is driven with a second pulse, and a voltage amplitude of said second pulse is larger than a voltage amplitude of said first pulse.

2. A semiconductor device according to claim 1, further comprising:

a power-supply switch for a block including repetition circuits, wherein said power supply switch is said MOS transistor.

3. A semiconductor device according to claim 1, further comprising:

a power-supply switch which is connected to each of a plurality of sub-blocks and is selectively activated,

wherein the power supply switch is said MOS transistor.

4. A semiconductor device according to claim 1,

wherein said voltage amplitude of said second pulse is larger than a voltage amplitude of a drain or a source of said MOS transistor.

5. A semiconductor device according to claim 4, wherein in said MOS transistor, said first gate and said second gate are connected to each other through a circuit outputting said second pulse.

6. A semiconductor device according to claim 4, further comprising:

a power-supply switch for a block including repetition circuits, wherein said power supply switch is said MOS transistor.

7. A semiconductor device according to claim 4, further comprising:

a power-supply switch which is connected to each of a plurality of sub-blocks and is selectively activated,

wherein said power supply switch is said MOS transistor.