Precision oscillator having improved temperature coefficient control
First Claim
1. A free running clock circuit, comprising:
- a switching circuit for switching between first and second logic states at a predetermined frequency, said switching circuitry changing between said first and second logic states based upon a trip voltage, said switching circuitry having an programmable temperature profile associated therewith, said switching circuit comprising;
a comparator circuit that is comprised of first and second comparators, each of said first and second comparators having a reference input connected to receive said trip voltage with the output of each of said two comparators changing logic states between a first logic state and a second logic state when the other input thereof passes said trip voltage, the first and second comparators having a programmable offset voltage for programming the voltage supply profile of the switching circuit, wherein the first and second comparators further comprise;
a current mirror comprised of a first and second transistors responsive to the inputs of the comparator;
a source degeneration circuit connected to a source of each of the first and second transistors of the current mirror, the source degeneration circuit generating the programmable offset voltage responsive to control signals thereto, the source degeneration circuit further comprising;
a first plurality of triode transistors connected in parallel to a first side of the current mirror;
a second plurality of triode transistors connected in parallel to a second side of the current mirror;
an RC timing circuit for defining when each of said two comparators switches the outputs thereof by providing a feedback that is input to the other input of each of the two comparators; and
a temperature compensated trip voltage generator for outputting a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit.
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Accused Products
Abstract
A free running clock circuit includes a switching circuit for switching between first and second logic states at a predetermined frequency based upon a trip voltage the switching circuit has a programmable temperature profile associated therewith. The switching circuit includes a comparator circuit that has first and second comparators. The first and second comparators have a reference input connected to receive the trip voltage, and the output of the comparators change logic states between a first logic state and a second logic state when the other input of the comparator passes the trip voltage. The first and second comparators have a programmable offset voltage enabling programming of the programmable voltage supply profile of the switching circuit. An RC timing circuit defines when the outputs of the comparators switch between the first and second logic states by providing a feedback to the other inputs of the two comparators. A temperature compensated trip voltage generator outputs a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit.
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Citations
21 Claims
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1. A free running clock circuit, comprising:
a switching circuit for switching between first and second logic states at a predetermined frequency, said switching circuitry changing between said first and second logic states based upon a trip voltage, said switching circuitry having an programmable temperature profile associated therewith, said switching circuit comprising; a comparator circuit that is comprised of first and second comparators, each of said first and second comparators having a reference input connected to receive said trip voltage with the output of each of said two comparators changing logic states between a first logic state and a second logic state when the other input thereof passes said trip voltage, the first and second comparators having a programmable offset voltage for programming the voltage supply profile of the switching circuit, wherein the first and second comparators further comprise; a current mirror comprised of a first and second transistors responsive to the inputs of the comparator; a source degeneration circuit connected to a source of each of the first and second transistors of the current mirror, the source degeneration circuit generating the programmable offset voltage responsive to control signals thereto, the source degeneration circuit further comprising; a first plurality of triode transistors connected in parallel to a first side of the current mirror; a second plurality of triode transistors connected in parallel to a second side of the current mirror; an RC timing circuit for defining when each of said two comparators switches the outputs thereof by providing a feedback that is input to the other input of each of the two comparators; and a temperature compensated trip voltage generator for outputting a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated system on a chip with serial asynchronous communication capabilities, comprising:
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processing circuitry for performing predefined digital processing functions on the chip; a free running clock circuit for generating a temperature compensative clock, comprising; a switching circuit for switching between first and second logic states at a predetermined frequency, said switching circuitry changing between said first and second logic states based upon a trip voltage, said switching circuitry having an programmable temperature profile associated therewith, said switching circuit comprising; a comparator circuit that is comprised of first and second comparators, each of said first and second comparators having a reference input connected to receive said trip voltage with the output of each of said two comparators changing logic states between a first logic state and a second logic state when the other input thereof passes said trip voltage, the first and second comparators having a programmable offset voltage for programming the voltage supply profile of the switching circuit, wherein the first and second comparators further comprise; a current mirror comprised of a first and second transistors responsive to the inputs of the comparator; a source degeneration circuit connected to a source of each of the first and second transistors of the current mirror, the source degeneration circuit generating the programmable offset voltage responsive to control signals thereto, the source degeneration circuit further comprising; a first plurality of triode transistors connected in parallel to a first side of the current mirror; a second plurality of triode transistors connected in parallel to a second side of the current mirror; an RC timing circuit for defining when each of said two comparators switches the outputs thereof by providing a feedback that is input to the other input of each of the two comparators; and a temperature compensated trip voltage generator for outputting a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit; an asynchronous on-chip communication device for digitally communicating with an off-chip asynchronous communication device, which off-chip asynchronous communication device has an independent time reference, which communication between said on-chip communication device and said off-chip asynchronous communication device is effected without clock recovery, said asynchronous on-chip communication device having a time-base derived from said temperature compensated clock; and wherein said temperature compensated clock provides a time reference for both said processing circuitry and said asynchronous on-chip communication device. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A free running clock circuit, comprising:
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a switching circuit for switching between first and second logic states at a predetermined frequency, said switching circuitry changing between said first and second logic states based upon a trip voltage, said switching circuitry having an programmable temperature profile associated therewith, said switching circuit comprising; a comparator circuit that is comprised of first and second comparators, each of said first and second comparators having a reference input connected to receive said trip voltage with the output of each of said two comparators changing logic states between a first logic state and a second logic state when the other input thereof passes said trip voltage, wherein the first and second comparators further comprise; a current mirror comprised of a first and second transistors responsive to the inputs of the comparator; a source degeneration circuit connected to a source of each of the first and second transistors of the current mirror, the source degeneration circuit generating the programmable offset voltage responsive to control signals thereto, the source degeneration circuit further comprising; a first plurality of triode transistors connected in parallel to a first side of the current mirror; a second plurality of triode transistors connected in parallel to a second side of the current mirror; an RC timing circuit for defining when each of said two comparators switches the outputs thereof by providing a feedback that is input to the other input of each of the two comparators, wherein said RC timing circuit comprises; a first RC circuit and a second RC circuit; said first RC circuit and said second RC circuit each comprising a resistor connected through a switching device having an associated switch input between a first supply terminal and one side of a first variable capacitor array, the other side of said first variable capacitor array connected to another different supply terminal wherein current is switchable through said resistor to charge said first variable capacitor array; wherein the first variable capacitor array includes a course trim capacitor array and a fine trim capacitor array each programmable to control the programmable temperature profile of the switching circuit; a temperature compensated trip voltage generator for outputting a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit. - View Dependent Claims (18, 19, 20)
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21. A free running clock circuit, comprising:
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a switching circuit for switching between first and second logic states at a predetermined frequency, said switching circuitry changing between said first and second logic states based upon a trip voltage, said switching circuitry having an programmable temperature profile associated therewith, said switching circuit comprising; a comparator circuit that is comprised of first and second comparators, each of said first and second comparators having a reference input connected to receive said trip voltage with the output of each of said two comparators changing logic states between a first logic state and a second logic state when the other input thereof passes said trip voltage, the first and second comparators having a programmable offset voltage for programming the voltage supply profile of the switching circuit; an RC timing circuit for defining when each of said two comparators switches the outputs thereof by providing a feedback that is input to the other input of each of the two comparators, wherein said RC timing circuit comprises; a first RC circuit and a second RC circuit; said first RC circuit and said second RC circuit each comprising a resistor connected through a switching device having an associated switch input between a first supply terminal and one side of a first variable capacitor array, the other side of said first variable capacitor array connected to another different supply terminal wherein current is switchable through said resistor to charge said first variable capacitor array; wherein the first variable capacitor array includes a course trim capacitor array and a fine trim capacitor array each programmable to control the programmable temperature profile of the switching circuit;
wherein the fine trim capacitor array comprises both a binary coded capacitor array and a thermometer coded capacitor array;a temperature compensated trip voltage generator for outputting a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit.
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Specification