Reference voltage generators for use in display applications

• US 7,385,544 B2
• Filed: 03/01/2007
• Issued: 06/10/2008
• Est. Priority Date: 02/25/2005
• Status: Expired due to Fees

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Chia, Chor-Yin
• Primary Examiner(s): Nguyen; Khai M
• Application Number:
  US11/681,127
• Publication Number:
  US 20070146187A1
• Time in Patent Office: 467 Days
• Field of Search: 341/122, 341144-145, 345/98, 345/99, 345/100
• US Class Current: 341/144
• CPC Class Codes: G09G 2320/0673 for control of gamma adjustment, e.g. selecting another gamma curve
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers

Abstract

A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each sample-and-hold circuit in a first group of N sample-and-hold (S/H) circuits is connected to a corresponding output of the analog demultiplexer. Similarly, each S/H circuit in a second group of N S/H circuits is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the S/H circuits in the first group and a second input connected to an output of a corresponding one of the S/H circuits in the second group. N output buffers, each have an input connected to an output of a corresponding one of the N further multiplexers, and an output useful for driving a column driver.

Claims

1. A multi-reference voltage generator, comprising:

an interface controller having a serial data input and a parallel data output;

a first bank of N m-bit registers, said first bank of registers having a parallel data input connected to said parallel data output of said interface controller, where N is an integer ≧

2, and m is integer ≧

2;

a second bank of N m-bit registers, said second bank of registers also having a parallel data input connected to said parallel data output of said interface controller;

a first multiplexer having inputs connected to outputs of said first bank of registers and outputs of said second bank of registers;

an m-bit digital-to-analog (DAC) having an m-bit parallel input connected to an output of said first multiplexer;

an analog demultiplexer having an input connected to an analog output of said-bit DAC;

a first group of N sample-and-hold (S/H) circuits, wherein each S/H circuit in said first group is connected to a corresponding output of said analog demultiplexer;

a second group of N sample-and-hold (S/H) circuits, wherein each S/H circuit in said second group is connected to a corresponding output of said analog demultiplexer;

N further multiplexers, each of which has a first input connected to an output of a corresponding one of said S/H circuits in said first group and a second input connected to an output of a corresponding one of said S/H circuits in said second group; and

N output buffers, each of which has an input connected to an output of a corresponding one of said N further multiplexers, and an output useful for driving a column driver;

wherein said second bank of registers is written to while data in said first bank of registers is converted to analog voltages and stored in said first group of S/H circuits.

2. The multi-reference voltage generator of claim 1, wherein said first bank of registers is written to while data in said second bank of registers is converted to analog voltages and stored in said second group of S/H circuits.

3. The multi-reference voltage generator of claim 2, wherein, based on a select signal provided to said N further multiplexers, said N further multiplexers either provide analog voltages stored in said first group of S/H circuits, or analog voltages stored in said second group of S/H circuits, to said N output buffers.

4. The multi-reference voltage generator of claim 3, where N=14 and m=8.

5. The multi-reference voltage generator of claim 1, wherein control data received by said interface controller specifies whether data proceeding said control data is to be written to said first bank of registers or said second bank of registers.

6. The multi-reference voltage generator of claim 1, wherein:

the first bank of N m-bit registers stores N digital data values corresponding to a first gamma curve; and

the second bank of N m-bit registers stores N digital data values corresponding to a second gamma curve.

7. A multi-reference voltage generator, comprising:

an interface controller having a serial data input and a parallel data output;

a first bank of N m-bit registers, where N is an integer ≧

2, and m is integer ≧

2;

a second bank of N m-bit registers;

a digital demultiplexer that provides m-bits of data at a time, which are presented at said parallel data output of said interface controller, to one of said registers in said first bank or said second bank;

a first multiplexer having inputs connected to outputs of said first bank of registers and outputs of said second bank of registers;

an m-bit digital-to-analog converter (DAC) having an m-bit parallel input connected to an output of said first multiplexer;

an analog demultiplexer having an input connected to an analog output of said m-bit DAC;

a first group of N sample-and-hold (S/H) circuits, wherein each S/H circuit in said first group is connected to a corresponding output of said analog demultiplexer;

a second group of N sample-and-hold (S/H) circuits, wherein each S/H circuit in said second group is connected to a corresponding output of said analog demultiplexer;

N further multiplexers, each of which has a first input connected to an output of a corresponding one of said S/H circuits in said first group and a second input connected to an output of a corresponding one of said S/H circuits in said second group; and

N output buffers, each of which has an input connected to an output of a corresponding one of said N further multiplexers, and an output useful for driving a column driver;

wherein said second bank of registers is written to while data in said first bank of registers is converted to analog voltages and stored in said first group of S/H circuits.

8. The multi-reference voltage generator of claim 7, wherein said first bank of registers is written to while data in said second bank of registers is converted to analog voltages and stored in said second group of S/H circuits.

9. The multi-reference voltage generator of claim 8, wherein, based on a select signal provided to said N further multiplexers, said N further multiplexers either provide analog voltages stored in said first group of S/H circuits, or analog voltages stored in said second group of S/H circuits, to said N output buffers.

10. The multi-reference voltage generator of claim 9, where N=14 and m=8.

11. The multi-reference voltage generator of claim 7, wherein control data received by said interface controller specifies whether data proceeding said control data is to be written to said first bank of registers or said second bank of registers.

12. The multi-reference voltage generator of claim 7, wherein:

the first bank of N m-bit registers stores N digital data values corresponding to a first gamma curve; and

the second bank of N m-bit registers stores N digital data values corresponding to a second gamma curve.

13. A multi-reference voltage generator, comprising:

an interface controller having a serial data input and a parallel data output;

a first bank of N m-bit registers, where N is an integer ≧

2, and m is integer ≧

2;

a second bank of N m-bit registers;

a means for providing m-bits of data at a time, which are presented at said parallel data output of said interface controller, to one of said registers in said first bank or said second bank;

a first m-bit digital-to-analog converter (DAC) that converts digital data in a selected one of said registers of said first bank into an analog voltage;

a second m-bit digital-to-analog converter (DAC) that converts digital data in a selected one of said registers of said second bank into an analog voltage;

an analog demultiplexer having a first input connected to an analog output of said first m-bit DAC and a second input connected to an analog output of said second m-bit DAC;

a first group of N sample-and-hold (S/H) circuits, wherein each S/H circuit in said first group is connected to a corresponding output of said analog demultiplexer;

a second group of N sample-and-hold (S/H) circuits, wherein each S/H circuit in said second group is connected to a corresponding output of said analog demultiplexer;

N multiplexers, each of which has a first input connected to an output of a corresponding one of said S/H circuits in said first group and a second input connected to an output of a corresponding one of said S/H circuits in said second group; and

N output buffers, each of which has an input connected to an output of a corresponding one of said N further multiplexers, and an output useful for driving a column driver;

wherein said second bank of registers is written to while data in said first bank of registers is converted to analog voltages by said first DAC and stored in said first group of S/H circuits; and

wherein said first bank of registers is written to while data in said second bank of registers is converted to analog voltages by said second DAC and stored in said second group of S/H circuits;

wherein said second bank of registers is written to while data in said first bank of registers is converted to analog voltages and stored in said first group of S/H circuit.

14. The multi-reference voltage generator of claim 13, wherein said first bank of registers is written to while data in said second bank of registers is converted to analog voltages and stored in said second group of S/H circuits.

15. The multi-reference voltage generator of claim 14, wherein, based on a select signal provided to said N further multiplexers, said N further multiplexers either provide analog voltages stored in said first group of S/H circuits, or analog voltages stored in said second group of S/H circuits, to said N output buffers.

16. The multi-reference voltage generator of claim 15, where N=14 and m=8.

17. The multi-reference voltage generator of claim 13, wherein control data received by said interface controller specifies whether data proceeding said control data is to be written to said first bank of registers or said second bank of registers.

18. The multi-reference voltage generator of claim 13, wherein:

the first bank of N m-bit registers stores N digital data values corresponding to a first gamma curve; and

the second bank of N m-bit registers stores N digital data values corresponding to a second gamma curve.