Membrane 3D IC fabrication

• US 7,385,835 B2
• Filed: 12/18/2003
• Issued: 06/10/2008
• Est. Priority Date: 04/08/1992
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J
• Primary Examiner(s): Wilczewski; M.
• Application Number:
  US10/741,647
• Publication Number:
  US 20050082626A1
• Time in Patent Office: 1,636 Days
• Field of Search: 250/338.4, 250/370.01, 250/552, 365/51, 365/63, 365/114
• US Class Current: 365/114
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/136281 having a transmissive semiconductor substrate
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5387 : Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 148/135 : Removal of substrate
• CPC Class Codes: Y10S 438/928 : Front and rear surface processing
• CPC Class Codes: Y10S 438/938 : Lattice strain control or utilization
• CPC Class Codes: Y10S 438/942 : Masking
• CPC Class Codes: Y10S 438/967 : Semiconductor on specified insulator
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49162 : by using wire as conductive path
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49171 : with encapsulating
• CPC Class Codes: Y10T 29/4921 : with bonding

Abstract

General purpose methods for the fabrication of 5 integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially forced from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D 1C fabrication.

Claims

1. A method of information processing using overlying integrated circuits, at least two of the integrated circuits each comprising a transparent stress-controlled dielectric layer, the method comprising:

transferring information horizontally through horizontal transmission paths;

transferring information vertically between the at least two of the integrated circuits through vertical transmission paths; and

at least one of (1) processing the information on at least one of the at least two of the integrated circuits and (2) storing the information on at least one of the at least two of the integrated circuits.

2. The method of claim 1, wherein the vertical transmissions paths are electrical.

3. The method of claim 1, wherein the vertical transmissions paths are optical.

4. The method of claim 1, wherein the stress-controlled dielectric layer has a stress of at least one of less than about 8×

10⁸ dynes/cm² and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.

5. The method of claim 4, wherein said stress is tensile.

6. The method of claim 1, wherein the stress-controlled dielectric layer is at least one of elastic and substantially flexible.

7. The method of claim 1, wherein the stress-controlled dielectric layer is a low stress dielectric layer.

8. The method of claim 7, wherein the low stress dielectric layer has a stress of at least one of less than about 8×

10⁸ dynes/cm² and 2 to 100 times less than the fracture strength of the low stress dielectric layer.

9. The method of claim 8, wherein said stress is tensile.

10. The method of claim 7, wherein the low stress dielectric layer is at least one of elastic and substantially flexible.

11. The method of claim 1, wherein at least one of the overlying integrated circuits is thinned.

12. The method of claim 11, wherein the thinned integrated circuit has a thickness of less than about 50 microns.

13. The method of claim 11, wherein the at least one thinned integrated circuit is substantially flexible.

14. The method of claim 1, wherein the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.

15. The method of claim 14, wherein the inorganic dielectric material is at least in part at least one of an oxide of silicon, a nitride of silicon, silicon dioxide and silicon nitride.

16. The method of claim 1, further comprising forming the stress-controlled dielectric layer by depositing one or more stress-controlled dielectric films.

17. The method of claim 16, further comprising depositing at least one of the one or more stress-controlled dielectric films using at least one of a RF power source, multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.

18. The method of claim 1, further comprising forming a plurality of interconnect conductors within the stress-controlled dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.

19. The method of claim 1, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

20. The method of claim 1, comprising forming the stress-controlled dielectric layer at a temperature of about 400°

C.

21. The method of claim 1, further comprising forming at least one of the overlying integrated circuits on a substrate, wherein the substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

22. The method of claim 1, wherein the at least one of the overlying integrated circuits is able to be thinned to less than about 50 microns.

23. The method of claim 1, wherein at least one of the vertical transmission paths passes through at least one of the integrated circuits.