Method and system for detecting false packets in wireless communications systems
First Claim
Patent Images
1. A method for detecting a false packet, the method comprising:
- receiving a transmission;
accessing bit information regarding a plurality of fields of a valid packet, wherein each field includes at least one predetermined bit, and wherein the bit information includes legal values for the predetermined bits as set by a networking standard, wherein the predetermined bits include at least one of a rate bit, a length bit, a reserved bit, and a service bit;
identifying bits of the transmission;
comparing identified bits of the transmission to the legal values for the predetermined bits; and
rejecting the identified bits as a false packet if a comparison of the identified bits and the legal values do not match.
2 Assignments
0 Petitions
Accused Products
Abstract
Specific bits of an incoming transmission are compared against a predetermined bit pattern. If the selected bits do not match the predetermined bit pattern, then the incoming transmission is rejected as a false packet. The predetermined bit pattern can include legal values for predetermined bits in a plurality of fields. Notably, these legal values are set by a networking standard. A parity check may check may be performed in addition to checking for predetermined bits in other fields. A user interface can be used to determine the predetermined bit pattern.
21 Citations
82 Claims
-
1. A method for detecting a false packet, the method comprising:
-
receiving a transmission; accessing bit information regarding a plurality of fields of a valid packet, wherein each field includes at least one predetermined bit, and wherein the bit information includes legal values for the predetermined bits as set by a networking standard, wherein the predetermined bits include at least one of a rate bit, a length bit, a reserved bit, and a service bit; identifying bits of the transmission; comparing identified bits of the transmission to the legal values for the predetermined bits; and rejecting the identified bits as a false packet if a comparison of the identified bits and the legal values do not match. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 79, 80)
-
-
36. A device for detecting a false packet, the device comprising:
-
a receiver configured to receive incoming transmissions; a bit recognition device configured to recognize selected bits from an incoming transmission; storage for bit information regarding a plurality of fields of a valid packet, wherein each field includes at least one predetermined bit, and wherein the bit information includes legal values for the predetermined bits as set by a networking standard, said predetermined bits comprising at least one of a data rate bit, a length bit, and another predetermined bit, and said storage comprising a register configured to store the legal values; a comparator configured to compare the selected bits to the legal values, said comparator comprising a logic device configured to compare the legal values against at least one of the selected bits; and a rejection device configured to reject the incoming transmission if the selected bits do not match the legal values. - View Dependent Claims (37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60)
-
-
61. A computer readable media having instructions stored thereon that, when loaded into a computer, cause the computer to perform steps comprising:
-
accessing bit information regarding a plurality of fields of a valid packet, wherein each field includes at least one predetermined bit, and wherein the bit information includes legal values for the predetermined bits as set by a networking standard, wherein said predetermined bits include at least one of a rate bit, a length bit, a reserved bit, and a service bit; and loading the legal values into a register, wherein said register is coupled to a packet screening device that validates incoming packets by comparing the incoming packets to the legal values. - View Dependent Claims (62, 63, 64, 65, 66)
-
-
67. A device, comprising:
-
means for receiving a transmission; means for accessing bit information regarding a plurality of fields of a valid packet, wherein each field includes at least one predetermined bit, and wherein the bit information includes legal values for the predetermined bits as set by a networking standard, wherein the predetermined bits include at least one of a length bit, a rate bit, a reserved bit, and a service bit; means for comparing identified bits of the transmission to the legal values to determine if the identified bits are part of a valid packet; and means for rejecting the identified bits as a false packet if a comparison of the identified bits and the legal values do not match. - View Dependent Claims (68, 69, 70, 71, 72, 73, 74, 75, 76, 81, 82)
-
-
77. A method comprising the steps of:
-
receiving a transmission; identifying predetermined bits of the transmission; comparing identified bits to legal values to determine if the identified bits are part of a valid packet; and rejecting the identified bits as a false packet if comparison of the identified bits and the legal values do not match; wherein; said step of identifying comprises identifying at least one predetermined bit of the transmission that is not a parity bit; said step of comparing does not include parity bit calculations; said legal values include patterns determined by other than parity calculations; said step of rejecting comprises, rejecting an incoming packet associated with the identified bits as the false packet, clearing a line busy signal used by one of a receiver and a transmitter; and resetting a receiver device that receives transmissions; said legal values comprise set bit values and ranges of bit values corresponding to the identified bits; the identified bits comprise rate bits, length bits, reserved bits, service bits, and parity bits having set bit values and ranges of values; said set bit values and said ranges of values are based on at least one of a packet protocol standard, a device standard, and an implementation specific standards of a communications system receiving said transmission; said method further comprises the step of setting the legal values based on a user input, including the steps of, displaying a user interface, retrieving user inputs regarding the set bit values and the ranges of values of the legal values, storing the legal values, and running a program that performs a step of writing the legal values to a register for use by said comparing step; said transmission is a wireless OFDM 802.11a packet transmission; and said legal values corresponds to selected bits from an 802.11a packet.
-
-
78. A device, comprising:
-
a receiver configured to receive incoming transmissions; a bit slice recognizer configured to recognize selected bits from an incoming transmission; a comparator configured to compare the selected bits to legal values; and a rejection device configured to reject the incoming transmission if the selected bits do not match the legal values; wherein; the incoming transmission comprises an OFDM encoded 802.11a wireless packet; said bit slice recognizer comprises a state machine configured to identify the selected bits from the incoming transmission; said rejection device comprises a Medium Access Control device; the device further comprises a packet reject line coupled between said comparator and said rejection device; said comparator is further configured to assert the packet reject line if the selected bits do not match the legal values; said rejection device is further configured to reject the incoming transmission if the packet reject line is asserted; said state machine is coupled to the incoming transmission and the packet reject line and configured to produce at least a part of a timing of a channel busy signal based on the incoming transmission and the packet reject line; the device further comprising a transmitter coupled to the channel busy signal; said transmitter is configured to allow transmissions based on the channel busy signal; said receiver is coupled to the packet reject line; said receiver is further configured to reset based on assertion of the packet reject line; said state machine is further configured to assert the channel busy signal when the receiver receives the incoming transmission and clear the channel busy line when the incoming transmission is rejected; said legal values comprise a predetermined value and a range of values for data rate bits, reserved bits, length bits, and service field bits; the device further comprising memory elements configured to store the selected bits; said comparator comprises, a register configured to store the legal values, and a logic device configured to compare stored values in the register to stored values in the memory elements; the comparison device is coupled to each memory element and each register location in the register; said bit slice recognizer is configured to recognize data rate bits, reserved bits, length bits, service field bits, and other predetermined bits in a packet of the incoming transmission; the device further comprising a demodulator configured to demodulate the received transmissions; said demodulator coupled to the packet reject line and further configured to reset if the packet reject line is asserted; the device further comprising an input mechanism configured to write the legal values in said register; said input mechanism includes software configured to query a user for the legal values and software to write the legal values to said register; and at least some of the legal values are written to said register in tabular format.
-
Specification