Method and system for high-speed software reconfigurable code division multiple access communication

• US 7,386,005 B2
• Filed: 11/13/2001
• Issued: 06/10/2008
• Est. Priority Date: 05/10/1999
• Status: Expired due to Fees

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Vanhoof, Jan, Lugil, Nico, Louveaux, Sebastien, Philips, Lieven, Borghs, Eric, Vandermot, Jurgen, Mertens, Carl
• Primary Examiner(s): Orgad; Edan
• Assistant Examiner(s): Wong; Blanche
• Application Number:
  US09/992,669
• Publication Number:
  US 20020196754A1
• Time in Patent Office: 2,401 Days
• Field of Search: 370/320, 370/335, 370/342, 370/441, 370/343, 370/479, 370/480, 370/464
• US Class Current: 370/464
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/7075 with code phase acquisition
• CPC Class Codes: H04B 1/7115 Constructive combining of multi-path signals, i.e. RAKE receivers
• CPC Class Codes: H04B 2201/7071 with dynamic control of receiver resources

Abstract

A communication device for W-CDMA signal transmission and reception has a W-CDMA transmitter having at least one of a first RAM and first registers, wherein the transmitter is configured to operate in accordance with first parameters. Further, the communication device has a W-CDMA receiver having at least one of a second RAM and second registers, wherein the receiver is configured to operate in accordance with second parameters, and signal acquisition component. A processor is in data communication with the W-CDMA transmitter, the W-CDMA receiver and the signal acquisition component, and configured to provide for software configuration of the first and second parameters.

Claims

1. A communication device for wideband code division multiple access (W-CDMA) signal transmission and reception, comprising:

a W-CDMA transmitter comprising at least one of a first RAM and first registers arranged to store first parameters so as to configure the transmitter'"'"'s operation;

a W-CDMA receiver comprising at least one of a second RAM and second registers arranged to store second parameters so as to configure the receiver'"'"'s operation;

a signal acquisition component; and

a processor in data communication with the W-CDMA transmitter, the W-CDMA receiver and the signal acquisition component, wherein the processor is configured to provide for software configuration of the first and second parameters;

wherein the receiver comprises;

a pulse shaping filter;

a level control block configured to receive an output from the pulse shaping filter;

a demodulator configured to receive an output from the level control block and track multi-path components received from a base station; and

a reference demodulator configured to receive the output from the level control block and configured to estimate noise;

wherein the demodulator comprises;

a Rake filter producing a signal at a chip rate which is a coherent accumulation of channel corrected multipath components resulting from one base station; and

a tracking unit using the signal at the chip rate for descrambling and despreading a plurality of waveform channels,

wherein the Rake filter comprises;

a FIFO to buffer samples at the chip rate coming from the level control block;

a delay line containing a plurality of registers, an input of the delay line being connected to an output of the FIFO;

a plurality of finger blocks, inputs of the finger blocks being connected to programmable tap positions on the delay line; and

a summer of complex outputs of the finger blocks at a chip rate.

2. The communication device of claim 1, wherein the signal acquisition component comprises a hardware initial synchronization block which has at least one of reprogrammable parameters and reprogrammable algorithms.

3. The communication device of claim 1, wherein the processor controls at least one of the first RAM and the first registers, and the second RAM and the second registers.

4. The communication device of claim 1, wherein the W-CDMA transmitter comprises a first programmable pulse shaping filter, and wherein the receiver comprises a second programmable pulse shaping filter.

5. The communication device of claim 4, wherein the first pulse shaping filter and the second pulse shaping filter are programmable to perform GMSK filtering, and wherein the transmitter and receiver are configured to interface with a GSM front-end.

6. The communication device of claim 5, wherein the processor performs a protocol in accordance with a GSM protocol stack.

7. The communication device of claim 1, wherein the processor, the transmitter and the receiver are configured for waveform processing of signals in accordance with a predetermined format, wherein the predetermined format is one of the following:

UMTS, Satellite UMTS, Galileo, GPS, IS-2000, IMT-2000, CDMA2000, IS-95, 3GPP, 3GPP2 and ARIB.

8. The communication device of claim 1, wherein the transmitter comprises at least one element which is one of the following:

synchronization hardware to slave transmit start epochs to events external to the transmitter;

a burst generator for realizing discontinuous transmissions;

a quadrature pseudo-noise (QPN) channel containing one or more spreaders with a predetermined amplification of an output signal;

a combiner to accumulate the QPN channel output signal;

a PN code generator;

a scrambling code generator;

a scrambler;

a combiner which accumulates a scrambling code output;

a pulse shaping oversampling filter; and

an NCO and upconverter for carrier precompensation.

9. The communication device of claim 8, wherein the PN code generator is configured as a RAM in which PN codes are downloaded under control of the processor.

10. The communication device of claim 8, wherein the scrambling code generator is configured as a programmable Gold Code generator.

11. The communication device of claim 8, wherein the QPN channel is configured to execute UMTS forward or return link transmission.

12. The communication device of claim 8, wherein an amplification of the spreader output is configured to perform a transmit power control.

13. The communication device of claim 1, wherein the transmitter comprises a time interpolator to perform sub-chip time alignments.

14. The communication device of claim 1, wherein the transmitter is configured for multi-code transmission.

15. The communication device of claim 1 wherein the receiver further comprises a downconverter connected to an input of the pulse shaping filter so as to interface at a front-end at an intermediate frequency.

16. The communication device of claim 1 wherein the receiver is configured to execute forward link and return link waveforms in accordance with a predetermined format, wherein the predetermined format is one of the following:

UMTS, Satellite UMTS, Galileo, GPS, IS-2000, IMT-2000, CDMA2000, IS-95, 3GPP, 3GPP2 and ARIB.

17. The communication device of claim 1 wherein the level control block is included in a runtime control ioop controlled by the processor.

18. The communication device of claim 1, wherein the finger blocks are respectively grouped in a first multipath group and a second multipath group, the Rake filter being configured to accumulate energies of the outputs of the first multipath group and the second multipath group, and to use the accumulated values to feed a time error detector of the a DLL used for time tracking.

19. The communication device of claim 1, wherein the Rake filter comprises memories to hold at least one of a spreading code for a channel correction pilot, a scrambling code for a channel correction pilot, a channel correction pilot symbol modulation, and a channel correction pilot symbol activities.

20. The communication device of claim 19, wherein the memories are controlled by the processor.

21. The communication device of claim 19, wherein the finger block comprises:

a channel correction pilot descrambler;

a channel correction pilot despreader connected to an output of the channel correction pilot descrambler;

a channel correction pilot filter connected to an output of the channel correction pilot despreader and performing a coherent channel correction pilot symbol accumulation over a programmable number of steps, and producing a weighted average on a programmable number of the coherent channel correction pilot symbol accumulation over a programmable number of steps;

a channel estimator connected to the channel correction pilot filter and generating a channel estimation at the chip rate and using outputs of the pilot filter;

a channel corrector connected to the channel estimator and performing a multiplication of an incoming stream with a complex conjugate of the channel estimation;

a calculator connected to the pilot filter and configured to calculate a slot energy;

a comparator connected to the calculator and configured to compare the slot energy with a programmable threshold; and

a circuit connected to the comparator and configured to force the channel estimation to zero if the threshold is not exceeded.

22. The communication device of claim 21, wherein the finger is configured for slow and fast fading compensation by programming the channel correction pilot filter for slow fading, the channel correction pilot filter performing a coherent accumulation over a slot, and performing a weighted average over previous-previous, previous, actual and next obtained slot values yielding a channel estimation per slot, which is applied by the channel corrector;

and for fast fading, the channel correction pilot filter performing a coherent accumulation over a slot, and then deriving channel estimations through interpolating consecutive the coherent accumulations over a slot, yielding channel estimations with sub-symbol timing, which are applied by the channel corrector.

23. The communication device of claim 1 wherein the reference demodulator comprises an accumulator of programmable length of absolute values of samples at a chip rate, and a low pass filter operating on the accumulator output.

24. The communication device of claim 1 wherein the reference demodulator is included in a runtime control loop controlled by the processor.

25. The communication device of claim 1 wherein the demodulator is configured to perform satellite diversity.

26. The communication device of claim 1, wherein the device is configured to perform ranging measurements to geostationary satellites.

27. The communication device of claim 1, wherein the processor is in direct data communication with the signal acquisition component.

28. A communication device for wideband code division multiple access (W-CDMA) signal transmission and reception, comprising:

a W-CDMA transmitter comprising at least one of a first RAM and first registers arranged to store first parameters so as to configure the transmitter'"'"'s operation;

a W-CDMA receiver comprising at least one of a second RAM and second registers arranged to store second parameters so as to configure the receiver'"'"'s operation;

a signal acquisition component; and

a processor in data communication with the W-CDMA transmitter, the W-CDMA receiver and the signal acquisition component, wherein the processor is configured to provide for software configuration of the first and second parameters;

wherein the receiver comprises;

a pulse shaping filter;

a level control block configured to receive an output from the pulse shaping filter;

a demodulator configured to receive an output from the level control block and track multi-path components received from a base station; and

a reference demodulator configured to receive the output from the level control block and configured to estimate noise;

wherein the level control block comprises;

a programmable shifter configured to receive an input from the pulse shaping filter and to perform coarse grain dynamic control;

a programmable multiplier configured to receive an input from the shifter and to perform fine grain dynamic control;

a first overflow counter configured to receive an input from the multiplier and to operate on a most significant bit and a second most significant bit;

a second overflow counter configured to receive an input from the multiplier and to operate on the second most significant bit and a third most significant bit; and

a saturation logic configured to receive an input from the multiplier and to operate to limit the input received from the multiplier.