Method and device for detecting pulses of an incident pulse signal of the ultra wideband type

• US 7,386,066 B2
• Filed: 09/26/2002
• Issued: 06/10/2008
• Est. Priority Date: 09/27/2001
• Status: Expired due to Fees

• Current Assignee: STMicroelectronics NV, STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics NV, STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Lebowsky, Fritz, Arnaud, Thierry, Helal, Didier
• Primary Examiner(s): Payne; David C.
• Assistant Examiner(s): Flores; Leon
• Application Number:
  US10/256,282
• Publication Number:
  US 20030086511A1
• Time in Patent Office: 2,084 Days
• Field of Search: 375/340, 324/309, 370/342, 370/484
• US Class Current: 375/340
• CPC Class Codes: H04B 1/71637 Receiver aspects H04B1/7183 takes precedence
• CPC Class Codes: H04B 1/7183 Synchronisation

Abstract

A detection device includes an antenna for receiving an incident signal, and for delivering a base signal. A comparator receives the base signal and provides an intermediate signal representative of the sign of the base signal relative to a reference signal. A sampling circuit samples the intermediate signal for providing a digital signal. A digital processing circuit correlates the digital signal with a predetermined correlation signal.

Claims

1. A method for detecting ultra wideband pulses of an incident pulse signal, the method comprising:

receiving the incident pulse signal and providing a base signal based upon the incident pulse signal;

providing an intermediate signal representative of a sign of the base signal relative to a reference signal;

sampling the intermediate signal for providing a digital signal, the sampling comprising a serial-to-parallel conversion for successively delivering at a deliver frequency Fe groups of N samples in parallel, the delivery frequency Fe corresponding to an effective sampling frequency of the intermediate signal equal to N*Fe; and

digitally processing the digital signal by correlating the digital signal with a correlation signal for detecting pulses of the received incident pulse signal.

2. A method according to claim 1, wherein the pulses of the incident pulse signal have a central frequency within a range of 2 to 4 GHz;

and wherein the effective sampling frequency is greater than 10 GHz.

3. A method according to claim 2, wherein N is an integer power of 2;

and wherein the effective sampling frequency is 20 GHz, with the delivery frequency Fe is 200 MHz.

4. A method according to claim 1, wherein the correlation signal is the same as the digital signal.

5. A method according to claim 4, wherein the pulses of the incident pulse signal are respectively contained in successive time windows of length T, this length corresponding to a window of N1 samples of the digital signal;

and wherein the correlating is between a first set of N1 samples of the digital signal and a second set of N1 samples of the digital signal.

6. A method according to claim 1, wherein the incident pulse signal results from transmission of an initial pulse signal comprising pulses having a theoretical shape;

and wherein the correlation signal comprises a reference correlation signal corresponding to a theoretical base signal arising from reception of a theoretical pulse having the theoretical shape.

7. A method according to claim 6, wherein the reference correlation signal is made up of N2 reference samples;

and wherein the correlating comprises a sliding correlation between the samples of the digital signal and the N2 reference samples.

8. A method according to claim 1, further comprising performing a series of coherent integrations of the digital signal.

9. A device for detecting ultra wideband pulses of an incident pulse signal, the device comprising:

input means for receiving the incident pulse signal and providing a base signal based upon the incident pulse signal;

preprocessing means connected to said input means for providing an intermediate signal representative of a sign of the base signal relative to a reference signal, and having a first input for receiving the base signal and a second input for receiving the reference signal;

sampling means connected to said preprocessing means for sampling the intermediate signal for providing a digital signal; and

digital processing means connected to said sampling means for correlating the digital signal with a correlation signal, the correlation signal being the same as the digital signal, the pulses of the incident pulse signal being respectively contained in successive time windows of length T, with this length corresponding to a window of N1 samples of the digital signal provided by said sampling means, the correlating being between a first set of N1 samples of the digital signal and a second set of N1 samples of the digital signal.

10. A device according to claim 9, wherein said sampling means is based upon a serial-to-parallel conversion for successively delivering at a delivery frequency Fe groups of N samples in parallel, the delivery frequency Fe corresponding to an effective sampling frequency of the intermediate signal equal to N*Fe.

11. A device according to claim 10, wherein said sampling means comprises:

a programmable clock circuit for receiving a base clock signal having the delivery frequency Fe, and for providing N elementary clock signals all having the delivery frequency Fe but temporally offset by 1/N*Fe with respect to each other;

a first set of N flip-flops connected to said programmable clock circuit and having respective inputs for receiving the intermediate signal, with each flip flop being controlled by a respective elementary clock signal, and said first set of N flip-flops providing N samples; and

an output register connected to said first set of N flip-flops and being controlled by the base clock signal for storing the N samples, and for providing the N samples in parallel at the delivery frequency.

12. A device according to claim 11, wherein said programmable clock circuit comprises a digital phase-locked loop comprising:

a programmable ring oscillator for providing the N elementary clock signals;

a second set of N flip-flops connected to said programmable ring oscillator and having respective inputs for receiving the base clock signal, with each flip-flop being controlled by a respective elementary clock signal; and

a control circuit connected to said second set of N flip-flops for receiving respective outputs therefrom.

13. A device according to claim 10, wherein the pulses of the incident pulse signal have a central frequency within a range of 2 to 4 GHz;

and wherein the effective sampling frequency is greater than 10 GHz.

14. A device according to claim 13, wherein N is an integer power of 2;

and wherein the effective sampling frequency is 20 GHz, with the delivery frequency Fe is 200 MHz.

15. A device according to claim 9, wherein said sampling means is implemented in CMOS technology.

16. A device according to claim 9, further comprising control means for placing said sampling means and said digital processing means into a standby mode during predetermined time intervals.

17. A device according to claim 9, wherein the incident pulse signal results from transmission of an initial pulse signal comprising pulses having a theoretical shape;

and wherein the correlation signal comprises a reference correlation signal corresponding to a theoretical base signal arising from reception of a theoretical pulse having the theoretical shape.

18. A device according to claim 17, wherein the reference correlation signal is made up of N2 reference samples;

and wherein the correlating comprises a sliding correlation between the samples of the digital signal and the N2 reference samples.

19. A device according to claim 18, wherein said digital processing means additionally performs a series of coherent integrations of the digital signal.

20. A terminal for detecting ultra wideband pulses of an incident pulse signal, the terminal comprising:

an antenna for receiving the incident pulse signal and providing a base signal based upon the incident pulse signal, the incident pulse signal resulting from transmission of an initial pulse signal comprising pulses having a theoretical shape;

an amplifier connected to said antenna for providing an intermediate signal representative of a sign of the base signal relative to a reference signal;

a sampling circuit connected to said amplifier for sampling the intermediate signal for providing a digital signal; and

a digital processing circuit connected to said sampling circuit for correlating the digital signal with a correlation signal, the correlation signal comprising a reference correlation signal corresponding to a theoretical base signal arising from reception of a theoretical pulse having the theoretical shape, the reference correlation signal being made up of N2 reference samples, and the correlating comprising a sliding correlation between the samples of the digital signal and the N2 reference samples.

21. A terminal according to claim 20, wherein said sampling circuit is based upon a serial-to-parallel conversion for successively delivering at a delivery frequency Fe groups of N samples in parallel, the delivery frequency Fe corresponding to an effective sampling frequency of the intermediate signal equal to N*Fe.

22. A terminal according to claim 21, wherein said sampling circuit comprises:

a programmable clock circuit for receiving a base clock signal having the delivery frequency Fe, and for providing N elementary clock signals all having the delivery frequency Fe but temporally offset by 1/N*Fe with respect to each other;

a first set of N flip-flops connected to said programmable clock circuit and having respective inputs for receiving the intermediate signal, with each flip flop being controlled by a respective elementary clock signal, and said first set of N flip-flops providing N samples; and

an output register connected to said first set of N flip-flops and being controlled by the base clock signal for storing the N samples provided by said first set of N flip-flops, and for providing the N samples in parallel at the delivery frequency.

23. A terminal according to claim 22, wherein said programmable clock circuit comprises a digital phase-locked loop comprising:

a programmable ring oscillator for providing the N elementary clock signals;

a second set of N flip-flops connected to said programmable ring oscillator and having respective inputs for receiving the base clock signal, with each flip-flop being controlled by a respective elementary clock signal; and

a control circuit connected to said second set of N flip-flops for receiving respective outputs therefrom.

24. A terminal according to claim 21, wherein the pulses of the incident pulse signal have a central frequency within a range of 2 to 4 GHz a few GHz;

and wherein the effective sampling frequency is greater than 10 GHz.

25. A terminal according to claim 24, wherein N is an integer power of 2;

and wherein the effective sampling frequency is 20 GHz, with the delivery frequency Fe is 200 MHz.

26. A terminal according to claim 20, further comprising a control circuit for placing said sampling circuit and said digital processing circuit into a standby mode during predetermined time intervals.

27. A terminal according to claim 20, wherein the correlation signal is the same as the digital signal.

28. A terminal according to claim 27, wherein the pulses of the incident pulse signal are respectively contained in successive time windows of length T, this length corresponding to a window of N1 samples of the digital signal provided by said sampling circuit;

and wherein the correlating is between a first set of N1 samples of the digital signal and a second set of N1 samples of the digital signal.

29. A terminal according to claim 20 wherein said digital processing circuit additionally performs a series of coherent integrations of the digital signal.

30. A terminal according to claim 20, wherein the incident pulse signals are generated by a wireless transmission system.

31. A device for detecting ultra wideband pulses of an incident pulse signal, the device comprising:

an input for receiving the incident pulse signal and providing a base signal based upon the incident pulse signal;

a preprocessor coupled to said input for providing an intermediate signal representative of a sign of the base signal relative to a reference signal, and having a first input for receiving the base signal and a second input for receiving the reference signal;

a sampler coupled to said preprocessor for sampling the intermediate signal for providing a digital signal, and operating based upon a serial-to-parallel conversion for successively delivering at a delivery frequency Fe groups of N samples in parallel, the delivery frequency Fe corresponding to an effective sampling frequency of the intermediate signal equal to N*Fe; and

a digital processor coupled to said sampler for correlating the digital signal with a correlation signal.

32. A device according to claim 31, wherein said sampler comprises:

a programmable clock circuit for receiving a base clock signal having the delivery frequency Fe, and for providing N elementary clock signals all having the delivery frequency Fe but temporally offset by 1/N*Fe with respect to each other;

a first set of N flip-flops coupled to said programmable clock circuit and having respective inputs for receiving the intermediate signal, with each flip flop being controlled by a respective elementary clock signal, and said first set of N flip-flops providing N samples; and

an output register coupled to said first set of N flip-flops and being controlled by the base clock signal for storing the N samples, and for providing the N samples in parallel at the delivery frequency.

33. A device according to claim 32, wherein said programmable clock circuit comprises a digital phase-locked loop comprising:

a programmable ring oscillator for providing the N elementary clock signals;

a second set of N flip-flops coupled to said programmable ring oscillator and having respective inputs for receiving the base clock signal, with each flip-flop being controlled by a respective elementary clock signal; and

a control circuit coupled to said second set of N flip-flops for receiving respective outputs therefrom.

34. A device according to claim 31, wherein the pulses of the incident pulse signal have a central frequency within a range of 2 to 4 GHz;

and wherein the effective sampling frequency is greater than 10 GHz.

35. A device according to claim 31, further comprising a controller for placing said sampler and said digital processor into a standby mode during predetermined time intervals.