Digital automatic gain control method and apparatus

• US 7,386,074 B1
• Filed: 10/06/2003
• Issued: 06/10/2008
• Est. Priority Date: 10/06/2003
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Redpine Signals Incorporated (Silicon Laboratories Incorporated)
• Inventors: Sankabathula, Dharani Naga Sailaja, Murali, Partha Sarathy, Venkatesh, Narasimhan, Rao, Satya
• Primary Examiner(s): DEPPE, BETSY LEE
• Application Number:
  US10/680,620
• Time in Patent Office: 1,709 Days
• Field of Search: 375/345, 455/232.1, 455/234.1, 455/245.1, 341/139, 330/254, 330/278
• US Class Current: 375/345
• CPC Class Codes: H03G 3/3068 Circuits generating control signals for both R.F. and I.F. stages
• CPC Class Codes: H03G 3/3078 Circuits generating control signals for digitally modulated signals

Abstract

An RF receiver which produces quadrature digitized outputs and has a gain control is coupled to a digital gain controller which converts the quadrature digitized outputs into an rms voltage, and iterates over a finite number of steps to quickly control the gain to a level sufficient to achieve subsequent digital signal processing without limitations caused by insufficient dynamic range or nonlinear saturation effects caused by insufficient signal or excessive signal at the A/D input, respectively.

Claims

1. A digital gain control system comprising:

an rms voltage converter receiving one or more digital inputs and forming an rms value; and

a digital gain controller including;

an iteration variable set to an initial value;

a digital gain value having n data bits, said digital gain value having a maximum value and a minimum value, the initial digital gain value being set to the median of said maximum value and said minimum value;

a correction value having an initial value which is half of said initial digital gain value;

an iteration controller which performs the following sequential steps m times, said m being an integer less than said n;

comparing the rms value from said rms voltage converter to a threshold voltage value;

adding said correction value to said digital gain value if said rms value is less than said threshold voltage value, or subtracting said correction value from said digital gain value if said rms value is greater than said threshold voltage value;

forming a new correction value for a subsequent iteration by halving said correction value.

2. The digital gain control system of claim 1 wherein said m is a system constant derived from:

Nbinary, the number of search bits;

η

, the dB/step gain of a receiver to be controlled by said digital gain value;

Ndata, the bitwidth of the output of an A/D converter sampling a signal amplified by a variable gain amplifier, said variable gain controlled by said digital gain value;

κ

, the number of A/D converters quantization steps required for digital signal processing.

3. The digital gain control system of claim 2 wherein said m is computed from:

m=Nbinary−

[log₂(10*log₁₀((2^Ndata−

1)/κ

η

)+1],

and the operator [.] rounds down to an integer value.

4. The digital gain control system of claim 1 wherein said correction value is 2⁽ⁿ⁻

k−

1) and said k is the number of times said iteration has been performed.

5. The digital gain control system of claim 1 wherein said correction value is positive.

6. The digital gain control system of claim 1 wherein said correction value is negative.

7. The digital gain control system of claim 1 wherein said iteration controller operates over a duration of time substantially equal to the duration of a received packet, said packet including a first interval and a second interval, the time duration between at least one said iteration during said first interval being less than the time duration between at least one said iteration during said second interval.

8. The digital gain control system of claim 7 wherein said first interval corresponds to a preamble interval of a wireless Ethernet packet.

9. The digital gain control system of claim 7 wherein said second interval corresponds to a payload interval following said first interval in a wireless Ethernet packet.

10. The process of claim 1 wherein said m is one of the values 3, 4, or 5.

11. A process for generating a value Vagc where said Vagc is a digital value having n bits and operative for controlling the gain of a processor which produces one or more channels of digital samples, said process comprising:

setting Vagc to an initial value;

setting Vcorrection to a value substantially equal to half of said Vagc initial value; and

performing the following first through fourth steps m iterations in sequence;

a first step of measuring said digital samples;

a second step of converting said digital samples into an rms value;

a third step of comparing said rms value with a threshold value and adding said Vcorrection to said Vagc if said rms value is less than said threshold value, and subtracting said Vcorrection from said Vagc if said rms value is greater than said threshold value;

a fourth step of forming a new value of said Vcorrection by halving the value of said Vcorrection.

12. The process of claim 11 wherein said m is a system constant derived from:

Nbinary, the number of search bits;

η

, the dB/step gain of a receiver to be controlled by said digital gain value;

Ndata, the bitwidth of the output of an A/D converter sampling a signal amplified by a variable gain amplifier, said variable gain controlled by said digital gain value;

κ

, the number of A/D converter quantization steps required for digital signal processing.

13. The process of claim 12 wherein said m is one of the values 3, 4, or 5.

14. The process of claim 12 whereby said m is computed from:

m=Nbinary−

[log₂(10*log₁₀((2^Ndata−

1)/κ

η

)+1]

and the operator [.] rounds down to an integer value.

15. The process of claim 11 wherein said Vagc has a maximum value of 2ⁿ−

1.

16. The process of claim 11 wherein said gain correction value is 2⁽ⁿ⁻

k−

1), and k is the number of the iteration, starting at 1 and incrementing by 1 for each said iteration.

17. The process of claim 11 wherein said Vcorrection value is positive.

18. The process of claim 11 wherein said Vcorrection value is negative.

19. The process of claim 11 wherein said first through fourth steps comprise an iteration time wherein the iteration time during a first interval is shorter than the iteration time during a second interval and wherein the second interval follows said first interval.

20. The process of claim 19 wherein said first interval corresponds to a preamble time T1 of a wireless Ethernet packet.

21. The process of claim 19 wherein said second interval corresponds to a frame time following the preamble time of a wireless Ethernet packet.

22. The process of claim 11 wherein said m iterations occurs during a preamble time of a wireless Ethernet packet.

23. An RF front end comprising:

an RF receiver responsive to a digital gain control input of width n bits, said RF receiver producing quadrature output digital values; and

a digital gain controller coupled to said digital gain control input and producing a digital output Vagc coupled to said digital gain control input in response to said quadrature output digital values, said output Vagc generated by;

setting Vagc to an initial value 2<sup>(n−

1)</sup>−

1 and setting an iteration variable k to 0;

performing the following first through fourth steps while said k is less than m, where said m is an integer less than said n;

a first step of measuring said quadrature output digital values and producing the rms value of said quadrature output digital values;

a second step of comparing said rms value to a threshold value;

a third step of incrementing said k;

a fourth step of adding a correction value 2<sup>(n−

k−

1)</sup> to said Vagc if said rms value is less than said threshold value, and subtracting a correction value 2<sup>(n−

k−

1)</sup> from said Vagc if said rms value is greater than said threshold value.

24. The RF front end of claim 23 wherein said m is a system constant derived from:

Nbinary, the number of search bits;

η

, the dB/step gain of a receiver to be controlled by said digital gain value;

Ndata, the bitwidth of the output of an A/D converter sampling a signal amplified by a variable gain amplifier, said variable gain controlled by said digital gain value;

κ

, the number of A/D converters quantization steps required for digital signal processing.

25. The process of claim 24 wherein said m is one of the values 3, 4, or 5.

26. The process of claim 24 whereby said m is computed from:

m=Nbinary−

[log₂(10*log₁₀((2^Ndata−

1)/κ

η

)+1] and the operator [.] rounds down to an integer value.

27. The RF front end of claim 23 wherein said correction value is positive.

28. The RF front end of claim 23 wherein said correction value is negative.

29. The RF front end of claim 23 wherein said first through fourth steps comprise an iteration time wherein the iteration time during a first interval is shorter than the iteration time during a second interval and wherein the second interval follows said first interval.

30. The RF front end of claim 29 wherein said first interval corresponds to a preamble time of a wireless Ethernet packet.

31. The RF front end of claim 29 wherein said second interval corresponds to a frame time following the preamble time of a wireless Ethernet packet.

32. The RF front end of claim 23 wherein said first through fourth steps occur during a preamble time of a wireless Ethernet packet.

33. A digital gain control system for a first and second stream of quadrature data, said first and said second stream of quadrature data multiplexed into a single alternating stream of data having an associated first stream interval and a second stream interval, the digital gain control system operative on said single stream of data and computing a gain control value for each said first and said second stream of quadrature data said digital gain control system including:

an rms voltage converter receiving one or more values from said single stream of data and forming an rms value; and

a digital gain controller including;

an iteration variable associated with each said stream of data, each said iteration variable set to an initial value;

a digital gain value for each said stream of data, each said digital gain value having n bits, said digital gain value having a maximum value and a minimum value, each said digital gain value being initially set to the median of said maximum value and said minimum value;

a correction value associated with each said stream of data, each said correction value having an initial value which is substantially half of the initial digital gain value associated with a corresponding said stream of data;

an iteration process which performs the following sequential steps m times for each said stream of data;

comparing the rms value from said rms voltage converter for a particular stream of data to a threshold voltage value associated with said particular stream of data;

adding said correction value associated with said particular stream of data to said digital gain value if said rms value is less than said threshold voltage level associated with said particular stream of data, or subtracting said correction value associated with said particular stream of data from said digital gain value if said rms value is greater than said threshold voltage level associated with said particular stream of data;

forming a new correction value associated with said particular stream of data by halving said correction value associated with said particular stream of data;

whereby said digital gain control systems computes said first gain control value using only values from said first stream of data and computes said second gain control value using only values from said second stream of data.

34. The system of claim 33 wherein the iteration time for a particular said stream of data during a first interval is shorter than the iteration time during a second interval for said particular stream of data and wherein the second interval follows said first interval.

35. The system of claim 34 where said first interval corresponds to a preamble time of a wireless Ethernet packet.

36. The system of claim 34 where said second interval corresponds to a frame time following the preamble time of a wireless Ethernet packet.

37. The system of claim 33 where said m times occurs during a preamble time of a wireless Ethernet packet.

38. An RF front end comprising:

a first RF receiver having a digital gain control input of width n and producing a first quadrature output digital value including a first I value and a first Q value;

a second RF receiver having a digital gain control input of width n bits and producing a second quadrature output digital value including a second I value and a second Q value;

a multiplexer converting said first I value and said second I value into a stream of alternating first and second I values, and also converting said first Q value and said second Q value into a stream of alternating first and second Q values; and

a digital gain controller coupled to said stream of alternating I values and said stream of alternating Q values and producing a first output Vagc and a second output Vagc, respectively, each of said first Vagc and said second Vagc independently generated by;

setting Vagc to an initial value 2<sup>(n−

1)</sup>−

1, where n is said bit width, and setting an iteration variable k to 0;

performing the following steps while said k is less than said m;

a first step of measuring said quadrature digital values and producing the rms value of said quadrature digital values;

a second step of comparing said rms value to a threshold value;

a third step of incrementing said k; and

a fourth step of adding a correction value 2<sup>(n−

k−

1)</sup> to said Vagc if said rms value is less than said threshold value, and subtracting the correction value 2<sup>(n−

k−

1)</sup> from said Vagc if said rms value is greater than said threshold value.

39. The RF front end of claim 38 wherein said first through fourth steps comprise an iteration time wherein the iteration time during a first interval is shorter than the iteration time during a second interval and wherein the second interval follows said first interval.

40. The RF front end of claim 39 wherein said first interval corresponds to a preamble time of a wireless Ethernet packet.

41. The RF front end of claim 39 wherein said second interval corresponds to a frame time following the preamble time of a wireless Ethernet packet.

42. The RF front end of claim 39 wherein said first through fourth steps occur during a preamble time of a wireless Ethernet packet.

43. A process for generating a first value Vagc and a second value Vagc from an alternating stream of first quadrature data and second quadrature data, where said first Vagc is derived exclusively from said first quadrature data and said second Vagc is derived exclusively from said second quadrature data, where each of said first Vagc and said second Vagc are each digital values having n bits, said process comprising for each said first and second Vagc:

setting Vagc to a first value; and

setting Vcorrection to a value equal to substantially half of said Vagc first value;

performing the following steps m times in sequence;

measuring one or more said quadrature data samples and converting said quadrature data samples into an rms value;

comparing said rms value with a threshold value and

adding said Vcorrection to said Vagc if said rms value is less than said threshold value, and subtracting said Vcorrection from said Vagc if said rms value is greater than said threshold value;

forming a new value of said Vcorrection by halving the value of said Vcorrection.

44. The process of claim 43 wherein said first through fourth steps have an iteration time wherein the iteration time during a first interval is shorter than the iteration time during a second interval and wherein the second interval follows said first interval.

45. The process of claim 43 wherein said first interval corresponds to a preamble time of a wireless Ethernet packet.

46. The process of claim 43 wherein said second interval corresponds to a frame time following the preamble time of a wireless Ethernet packet.

47. The process of claim 43 wherein said m times occurs during a preamble time of a wireless Ethernet packet.