Method and system for pattern-independent phase adjustment in a clock and data recovery (CDR) circuit
First Claim
1. A system for pattern-independent phase alignment and adjustment in a clock and data recovery circuit, the system comprising:
- a data XOR gate coupled to a differential input data signal, said data XOR gate having a single output coupled to a bias voltage through a first variable resistor;
a reference XOR gate coupled to a latched differential input signal, said reference XOR gate having a single output coupled to said bias voltage through a second variable resistor; and
at least one latch coupled to at least one differential input of said data XOR gate and said reference XOR gate, wherein at least one of the following is adjusted;
a resistance ratio of said first variable resistor and said second variable resistor so that current pulses at an output of said data XOR gate and current pulses at an output of said reference XOR gate are equal for a desired phase relationship between a clock signal and a data signal; and
a current flowing through said first variable resistor so that no current flows at said single output of said data XOR gate when there are no transitions occurring at an input of said data XOR gate and a current flowing through said second variable resistor so that no current flows at said single output of said reference XOR gate when there are no transitions occurring at an input of said reference XOR gate.
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Abstract
Aspects of the pattern-independent phase adjustment system includes a single output data XOR gate coupled to a differential input data signal and a bias voltage through a first variable resistor. A single output reference XOR gate may be coupled to a latched differential input signal and the bias voltage through a second variable resistor. At least one latch may be coupled to at least one differential input of the data and reference XOR gate. The single output of the data XOR gate may be a data output of a clock and data recovery circuit (CDR) and the single output of the reference XOR gate may be a reference output of the clock and CDR. No current may flow at the data output of the data XOR gate and the reference output of the reference XOR gate when there are no transitions occurring at an input of the phase detector.
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Citations
7 Claims
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1. A system for pattern-independent phase alignment and adjustment in a clock and data recovery circuit, the system comprising:
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a data XOR gate coupled to a differential input data signal, said data XOR gate having a single output coupled to a bias voltage through a first variable resistor; a reference XOR gate coupled to a latched differential input signal, said reference XOR gate having a single output coupled to said bias voltage through a second variable resistor; and at least one latch coupled to at least one differential input of said data XOR gate and said reference XOR gate, wherein at least one of the following is adjusted; a resistance ratio of said first variable resistor and said second variable resistor so that current pulses at an output of said data XOR gate and current pulses at an output of said reference XOR gate are equal for a desired phase relationship between a clock signal and a data signal; and a current flowing through said first variable resistor so that no current flows at said single output of said data XOR gate when there are no transitions occurring at an input of said data XOR gate and a current flowing through said second variable resistor so that no current flows at said single output of said reference XOR gate when there are no transitions occurring at an input of said reference XOR gate. - View Dependent Claims (2, 3)
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4. A method for pattern independent phase alignment and adjustment in a phase detector, the method comprising:
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generating a data output for the phase detector at only a negative output of a data XOR gate; generating a reference output for the phase detector at only a negative output of a reference XOR gate; and adjusting at least one of; a resistance of a resistive load coupled to said data output and said reference output; and a current flowing through said resistive load coupled to said data output and said reference output, so that no current flows at the data output of the data XOR gate and the reference output of the reference XOR gate when there are no transitions occurring at an input of the phase detector. - View Dependent Claims (5, 6, 7)
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Specification