Method and system for pattern-independent phase adjustment in a clock and data recovery (CDR) circuit

• US 7,386,084 B2
• Filed: 06/06/2003
• Issued: 06/10/2008
• Est. Priority Date: 11/06/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Yin, Guangming
• Primary Examiner(s): Corrielus; Jean B.
• Application Number:
  US10/456,803
• Publication Number:
  US 20040240598A1
• Time in Patent Office: 1,831 Days
• Field of Search: 375/371, 375/373, 375/375, 375/376, 327/147, 327/150, 327/156, 327/159
• US Class Current: 375/371
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Aspects of the pattern-independent phase adjustment system includes a single output data XOR gate coupled to a differential input data signal and a bias voltage through a first variable resistor. A single output reference XOR gate may be coupled to a latched differential input signal and the bias voltage through a second variable resistor. At least one latch may be coupled to at least one differential input of the data and reference XOR gate. The single output of the data XOR gate may be a data output of a clock and data recovery circuit (CDR) and the single output of the reference XOR gate may be a reference output of the clock and CDR. No current may flow at the data output of the data XOR gate and the reference output of the reference XOR gate when there are no transitions occurring at an input of the phase detector.

Claims

1. A system for pattern-independent phase alignment and adjustment in a clock and data recovery circuit, the system comprising:

a data XOR gate coupled to a differential input data signal, said data XOR gate having a single output coupled to a bias voltage through a first variable resistor;

a reference XOR gate coupled to a latched differential input signal, said reference XOR gate having a single output coupled to said bias voltage through a second variable resistor; and

at least one latch coupled to at least one differential input of said data XOR gate and said reference XOR gate, wherein at least one of the following is adjusted;

a resistance ratio of said first variable resistor and said second variable resistor so that current pulses at an output of said data XOR gate and current pulses at an output of said reference XOR gate are equal for a desired phase relationship between a clock signal and a data signal; and

a current flowing through said first variable resistor so that no current flows at said single output of said data XOR gate when there are no transitions occurring at an input of said data XOR gate and a current flowing through said second variable resistor so that no current flows at said single output of said reference XOR gate when there are no transitions occurring at an input of said reference XOR gate.

2. The system according to claim 1, wherein said single output of said data XOR gate is a data output of the clock and data recovery circuit.

3. The system according to claim 1, wherein said single output of said reference XOR gate is a reference output of the clock and data recovery circuit.

4. A method for pattern independent phase alignment and adjustment in a phase detector, the method comprising:

generating a data output for the phase detector at only a negative output of a data XOR gate;

generating a reference output for the phase detector at only a negative output of a reference XOR gate; and

adjusting at least one of;

a resistance of a resistive load coupled to said data output and said reference output; and

a current flowing through said resistive load coupled to said data output and said reference output, so that no current flows at the data output of the data XOR gate and the reference output of the reference XOR gate when there are no transitions occurring at an input of the phase detector.

5. The method according to claim 4, wherein said adjustment of said at least one of said resistance and said current causes no change in an output voltage at both the outputs of said data XOR gate and said reference XOR gate when there are no transitions occurring at said input of the phase detector.

6. The method according to claim 4, comprising generating a voltage pulse having a pulse height equivalent to a product of said resistance of said resistive load and an instantaneous pulse current flowing through said resistive load when there are transitions occurring at said input of the phase detector.

7. The method according to claim 4, comprising generating a pulse having a pulse width within a range zero (0) to T, where T represents a full bit period, when there are transitions occurring at an input of each of said data XOR gate and said reference XOR gate.