Data analysis method for integrated circuit process and semiconductor process

• US 7,386,420 B2
• Filed: 06/02/2006
• Issued: 06/10/2008
• Est. Priority Date: 06/02/2006
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Du, Lu-Ying, Zhang, Guohai, Lee, Kay-Ming, Kuo, Jui-Chun
• Primary Examiner(s): TSAI, CAROL S W
• Application Number:
  US11/308,986
• Publication Number:
  US 20070282544A1
• Time in Patent Office: 739 Days
• Field of Search: 702/35, 702/82, 702/83, 702/84, 702/179, 702/180, 702/181, 438 14- 18, 700/108, 700/109, 700/110, 700/111, 700/121, 714/37, 714/48
• US Class Current: 702/179
• CPC Class Codes: G05B 19/41875 characterised by quality surveillance of production
• CPC Class Codes: G05B 2219/32222 Fault, defect detection of origin of fault, defect of product
• CPC Class Codes: G05B 23/0294 Optimizing process, e.g. process efficiency, product quality
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A data analysis method for an integrated circuit process is described, for analyzing the results of at least an in-line quality test, a product test and a yield test done to the products of the IC process. The products are divided into a normal group and an abnormal group based on the result of the in-line quality test, and are divided into a qualified group and an unqualified group based on the result of the yield test. A categorization step is performed to define the intersection of the unqualified group and the normal group as a first problematic group and to define the intersection of the unqualified group and the abnormal group as a second problematic group. By analyzing one or both of the two problematic groups, the major yield killer can be identified so that process modification can be made accordingly to improve the yield.

Claims

1. A data analysis method for an IC process, used to analyze results of at least an in-line quality test, a product test and a yield test conducted to a plurality of products of the IC process, comprising:

dividing the products into a normal group and an abnormal group based on the result of the in-line quality test;

dividing the products into a qualified group and an unqualified group based on the result of the yield test; and

conducting a categorization step to define an intersection of the unqualified group and the normal group as a first problematic group and to define an intersection of the unqualified group and the abnormal group as a second problematic group.

2. The data analysis method of claim 1, further comprising:

determining, among the first and the second problematic groups, the group including a larger number of products as a target group.

3. The data analysis method of claim 2, further comprising:

making a statistical analysis to test data of the products in the first problematic group obtained in the product test and in the yield test when the first problematic group is the target group, so as to identify a major yield killer of the IC process.

4. The data analysis method of claim 3, wherein the products comprise a plurality of dies on a wafer.

5. The data analysis method of claim 4, wherein the in-line quality test comprises a defect inspection.

6. The data analysis method of claim 5, wherein the product test comprises a wafer acceptance test (WAT).

7. The data analysis method of claim 2, further comprising:

making a statistical analysis to test data of the products in the second problematic group obtained in the in-line quality test when the second problematic group is the target group, so as to identify a major yield killer of the IC process.

8. The data analysis method of claim 1, further comprising:

making a statistical analysis to test data of the products in the first problematic group obtained in the product test and in the yield test as well as making another statistical analysis to test data of the products in the second problematic group obtained in the in-line quality test, so as to identify a major yield killer of the IC process.

9. The data analysis method of claim 1, wherein the products comprise a plurality of dies on a wafer.

10. The data analysis method of claim 9, wherein the in-line quality test comprises a defect inspection, a critical dimension inspection, an alignment accuracy inspection, a thickness inspection and an electrical property test.

11. A data analysis method for a semiconductor process, used to analyze results of at least a defect inspection, a wafer acceptance test (WAT) and a yield test conducted to a wafer that has been subject to a plurality of fabricating steps and having a plurality of dies thereon, comprising:

dividing the dies into a normal group and an abnormal group based on the result of the defect inspection;

dividing the dies into a qualified group and an unqualified group based on the result of the yield test; and

performing a categorization step to define an intersection of the unqualified group and the normal group as a first problematic group and to define an intersection of the unqualified group and the abnormal group as a second problematic group.

12. The data analysis method of claim 11, further comprising:

determining, among the first and the second problematic groups, the group including a larger number of dies as a target group.

13. The data analysis method of claim 12, further comprising:

making a statistical analysis to test data of the dies in the first problematic group obtained in the wafer acceptance test (WAT) and in the yield test when the first problematic group is the target group, so as to identify a major yield killer of the semiconductor process.

14. The data analysis method of claim 12, further comprising:

making a statistical analysis to test data of the dies in the second problematic group obtained in the defect inspection when the second problematic group is the target group, so as to identify a major yield killer of the semiconductor process.

15. The data analysis method of claim 11, further comprising:

making a statistical analysis to test data of the dies in the first problematic group obtained in the wafer acceptance test (WAT) and in the yield test as well as making another statistical analysis to test data of the dies in the second problematic group obtained in the defect inspection, so as to identify a major yield killer of the semiconductor process.