Multiple processor system and method including multiple memory hub modules
First Claim
1. A memory system, comprising:
- a plurality of memory requestors;
a first rank of memory modules coupled to the memory requestors, each of the memory modules in the first rank being coupled to a plurality of the memory requestors, each of the memory modules comprising;
a plurality of memory devices; and
a memory hub comprising;
a plurality of memory controllers, each of the memory controllers being coupled to at least one of the memory devices;
a first plurality of link interfaces, each of the link interfaces being coupled to a respective one of the memory requestors; and
a cross bar switch having a first plurality of switch ports, a second plurality of switch ports, and a plurality of memory ports, each of the switch ports being coupled to a respective one of the link interfaces, and each of the memory ports being coupled to a respective one of the memory controllers, the cross bar switch being operable to selectively couple each of the link interfaces to any one of the memory controllers; and
a second plurality of link interfaces each of which is coupled to a respective one of the switch ports in the second plurality of switch ports;
a second rank of memory modules each of which is coupled to a respective one of the second link interfaces in each of the memory modules in the first rank, each of the memory modules in the second rank comprising;
a plurality of memory devices; and
a memory hub comprising;
a plurality of memory controllers, each of the memory controllers being coupled to at least one of the memory devices;
a first plurality of link interfaces, each of the link interfaces being coupled to a respective one of the second link interfaces; and
a cross bar switch having a first plurality of switch ports and a plurality of memory ports, each of the switch ports being coupled to a respective one of the link interfaces in the first plurality, each of the memory ports being coupled to a respective one of the memory controllers, the cross bar switch being operable to selectively couple each of the link interfaces in the first plurality to any one of the memory controllers.
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Accused Products
Abstract
A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.
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Citations
21 Claims
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1. A memory system, comprising:
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a plurality of memory requestors; a first rank of memory modules coupled to the memory requestors, each of the memory modules in the first rank being coupled to a plurality of the memory requestors, each of the memory modules comprising; a plurality of memory devices; and a memory hub comprising; a plurality of memory controllers, each of the memory controllers being coupled to at least one of the memory devices; a first plurality of link interfaces, each of the link interfaces being coupled to a respective one of the memory requestors; and a cross bar switch having a first plurality of switch ports, a second plurality of switch ports, and a plurality of memory ports, each of the switch ports being coupled to a respective one of the link interfaces, and each of the memory ports being coupled to a respective one of the memory controllers, the cross bar switch being operable to selectively couple each of the link interfaces to any one of the memory controllers; and a second plurality of link interfaces each of which is coupled to a respective one of the switch ports in the second plurality of switch ports; a second rank of memory modules each of which is coupled to a respective one of the second link interfaces in each of the memory modules in the first rank, each of the memory modules in the second rank comprising; a plurality of memory devices; and a memory hub comprising; a plurality of memory controllers, each of the memory controllers being coupled to at least one of the memory devices; a first plurality of link interfaces, each of the link interfaces being coupled to a respective one of the second link interfaces; and a cross bar switch having a first plurality of switch ports and a plurality of memory ports, each of the switch ports being coupled to a respective one of the link interfaces in the first plurality, each of the memory ports being coupled to a respective one of the memory controllers, the cross bar switch being operable to selectively couple each of the link interfaces in the first plurality to any one of the memory controllers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A memory system, comprising:
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a plurality of memory requestors; a first rank of memory modules coupled to the memory requestors, the memory modules in the first rank each including a first set of memory ports corresponding in number to the number of memory requestors, each of the memory ports in the first rank being coupled to a respective one of the memory requestors, the memory modules in the first rank further including a second set of memory ports, each of the memory modules in the first rank including a plurality of memory devices and a memory hub coupled to the memory devices and to the memory ports in the first and second sets; and a second rank of memory modules each including at least one memory port coupled to a memory module in the first rank through a memory port in the second set, each of the memory modules in the second rank including a plurality of memory devices and a memory hub coupled to the memory devices and to the at least one memory port, at least one of the memory modules in the second rank being accessed by at least one of the memory requestors through at least one of the memory modules in the first rank. - View Dependent Claims (14, 15, 16, 17)
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18. A method of accessing memory devices from a plurality of memory request ports, the method comprising:
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arranging a first plurality of memory modules in a first rank, each of the memory modules in the first rank including a plurality of memory devices; arranging a second plurality of memory modules in a second rank, each of the memory modules in the second rank including a plurality of memory devices; accessing each of the memory modules in the first rank from any of the memory request ports; and accessing each of the memory modules in the second rank from any of the memory request ports through at least one of the memory modules in the first rank. - View Dependent Claims (19, 20, 21)
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Specification