User-configurable pre-recorded memory

• US 7,386,652 B2
• Filed: 11/15/2005
• Issued: 06/10/2008
• Est. Priority Date: 04/04/2004
• Status: Active Grant

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Sparks, Donald
• Assistant Examiner(s): Bertram, Ryan
• Application Number:
  US11/164,246
• Publication Number:
  US 20060085615A1
• Time in Patent Office: 938 Days
• Field of Search: 711/168
• US Class Current: 711/101
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 21/10 Protecting distributed programs or content, e.g. vending or licensing of copyrighted material protection in video systems or pay television H04N7/16 ; Digital rights management [DRM]
• CPC Class Codes: G06F 21/62 Protecting access to data via a platform, e.g. using keys or access control rules
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: G06F 2221/2137 Time limited access, e.g. to a computer or data
• CPC Class Codes: G06F 2221/2141 Access rights, e.g. capability lists, access control lists, access tables, access matrices
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence

Abstract

In a user-configurable pre-recorded memory (UC-PM), a user can select contents he is interested in, and pay copyright fees accordingly. With large capacity, low cost and great integratibility, 3D-M, more particularly 3D-MPM, is suitable for UC-PM. It provides excellent access control and impenetrable copyright protection. UC-PM will enable a copyright distribution model fair to both copyright holders and users. On the other hand, the 3D-MPM scaling should be the fastest among all memory types.

Claims

1. A narrow-line three-dimensional memory (3D-M), comprising:

a substrate having a transistor-based memory, said transistor-based memory comprising a plurality of transistors and a plurality of first address-selection lines in parallel; and

a diode-based memory stacked above said substrate and coupled to said substrate through a plurality of inter-level vias, said diode-based memory comprising a plurality of diodes and a plurality of second address-selection lines in parallel;

wherein said diode-based memory comprises no transistors, and the minimum pitch of said second address-selection lines is smaller than the minimum pitch of said first address-selection lines.

2. The narrow-line 3D-M according to claim 1, wherein the size of said inter-level vias is larger than the minimum half-pitch of said second address-selection lines.

3. The narrow-line 3D-M according to claim 1, wherein said diode-based memory is a mask-programmable memory.

4. The narrow-line 3D-M according to claim 3, wherein said mask-programmable memory comprises no antifuse.

5. The narrow-line 3D-M according to claim 3, wherein the size of said inter-level vias is larger than the minimum half-pitch of said second address-selection lines.