Non-volatile configuration data storage for a configurable memory

• US 7,386,654 B2
• Filed: 10/15/2004
• Issued: 06/10/2008
• Est. Priority Date: 10/15/2004
• Status: Active Grant

• Current Assignee: Intel NDTM US LLC (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Larsen, Robert E., Rajguru, Chaitanya S., Dover, Lance W.
• Primary Examiner(s): ELMORE, STEPHEN C
• Application Number:
  US10/966,183
• Publication Number:
  US 20060083093A1
• Time in Patent Office: 1,334 Days
• Field of Search: 711/103, 711/104, 711/105, 711/154, 711/170, 713/1, 713/2
• US Class Current: 711/103
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

Various embodiments of the invention may provide one or more non-volatile storage entities, such as a register or a storage array, to store configuration information for a memory device. The specified configuration may then be enabled at the occurrence of a specified event, such as power-up and/or reset.

Claims

1. An apparatus comprising

a memory device comprising:

a memory array; and

a writable non-volatile storage element coupled to the memory array, the non-volatile storage element to hold contents defining operational configuration parameters of the memory device;

wherein the non-volatile storage element comprises multiple non-volatile storage cells, an output of each non-volatile storage cell being coupled to an input of a volatile storage cell different than the volatile storage cells connected to other non-volatile storage cells.

2. The apparatus of claim 1, further comprising:

a volatile storage element; and

a circuit to store contents of at least a portion of the non-volatile storage element in the volatile storage element upon receipt of a particular signal.

3. The apparatus of claim 2, wherein:

the non-volatile storage element comprises a non-volatile storage array; and

the circuit comprises executable micro-code to read the contents from the non-volatile storage array and store the contents in the volatile storage element.

4. The apparatus of claim 1, wherein the non-volatile storage element comprises a non-volatile register.

5. The apparatus of claim 1, wherein the operational configuration parameters comprise indicators of at least one item selected from a list consisting of:

1) a synchronous or asynchronous interface,

     2) number of wait states to be observed during operation,

     3) polarity of a control signal,

     4) width of data to be read at one time from the memory device,

     5) polarity of an interrupt signal, and

     6) power mode to be implemented.

6. The apparatus of claim 1, wherein the memory array comprises a non-volatile memory array.

7. The apparatus of claim 6, wherein the non-volatile memory array comprises a flash memory array.

8. A system, comprising

a processor and a memory device coupled to the processor, the memory device comprising:

a memory array; and

a writable non-volatile storage element coupled to the memory array, the non-volatile storage element to hold contents defining operational configuration parameters of the memory device;

wherein the non-volatile storage element comprises a non-volatile register, each output of the non-volatile register coupled to an input of a volatile storage cell different than the volatile storage cells connected to other non-volatile storage cells.

9. The system of claim 8, further comprising:

a volatile storage element; and

a circuit to store contents of at least a portion of the non-volatile storage element in the volatile storage element upon receipt of a particular signal.

10. The system of claim 9, wherein:

the non-volatile storage element comprises a non-volatile storage array; and

the circuit comprises executable micro-code to read the contents from the non-volatile storage array and store the contents in the volatile storage element.

11. The system of claim 8, wherein the operational configuration parameters comprise indicators of at least one item selected from a list consisting of:

1) a synchronous or asynchronous interface,

     2) number of wait states to be observed during operation,

     3) polarity of a control signal,

     4) width of data to be read at one time from the memory device,

     5) polarity of an interrupt signal, and

     6) power mode to be implemented.