Method for allocating processor resources and system for encrypting data

• US 7,386,705 B2
• Filed: 08/27/2002
• Issued: 06/10/2008
• Est. Priority Date: 08/27/2002
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Hamilton, Neil Farquhar, Zaabab, Hafid, Low, Arthur John
• Primary Examiner(s): Chan; Eddie P
• Assistant Examiner(s): Fennema; Robert E
• Application Number:
  US10/228,933
• Publication Number:
  US 20040044898A1
• Time in Patent Office: 2,114 Days
• Field of Search: 712/34
• US Class Current: 712/34
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: H04L 2209/125 Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
• CPC Class Codes: H04L 63/0428 wherein the data content is protected, e.g. by encrypting or encapsulating the payload
• CPC Class Codes: H04L 9/06 the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators

Abstract

An apparatus for calculating and encryption of data has a multistage processing array and a plurality of registers. Each register has a status bit which indicates a “go” or “done” condition when the register is loaded. This enables the process array, after completion of a processing cycle, to connect to a “ready” register.

Claims

1. A system for encrypting data comprising:

a single multistage pipe-line encryption processor including a processor array of serial encryption processing stages configured to serially process independent blocks of data; and

,

a memory circuit in electrical communication with the processor array, the memory circuit including;

a first data storage area and a second data storage area for storing independent blocks of data for independent serial processing in the encryption processor;

a first status indicator storage location in each data storage area for storing a status indicator value for indicating that an independent block of data stored within the data storage area is ready for processing by the processor array, the status indicator value operable by a client station; and

a second status indicator storage location in each data storage area for storing a status indicator value for indicating completion of processing of an independent block of data stored within the data storage area, the second status indicator value operable by the encryption processor;

the memory circuit successively switching from a first mode to a second mode relative to the processor array, such that in a first mode the first data storage area is available to the encryption processor for processing a block of data and the second data storage area is available to a client station, and in the second mode the second data storage area is available to a client station and the first data storage area is available to the encryption processor for processing a block of data,

wherein prior to completing the serial processing of the current data within the first data storage area, the processor array determines a status of an indicator value within the first status indicator storage location for the second data storage, such that in use upon completion of processing the current data within the first data storage area and absent communication external to the encryption processor, the processor array immediately begins a subsequent serial processing operation of a subsequent independent block of data within the second data storage area in dependence upon the first indicator value in the second data storage area.

2. The system according to claim 1 wherein the indicator value is a bit.

3. The system according to claim 1 wherein the data storage area is a data bank.

4. The system according to claim 3 wherein a client station is in operative communication with the second data bank other than the data bank containing data currently being processed, for writing data to and from the second data bank.

5. The system according to claim 1 wherein the status indicator value in each data storage area is electrically coupled to a hardware selector for providing an electrical signal to the processor array, the electrical signal indicative of a next data storage area of data that is ready to be processed by the processor.

6. The system according to claim 5 comprising a next gate-logic circuit disposed between the processor array and the status indicator value in each data storage area, the next gate-logic circuit for, in use, receiving an electrical signal from a data storage area other than the data storage area data within which is currently being processed and for providing said electrical signal to the processor array at the end of a processing cycle.

7. The system according to claim 1 comprising at least one preference value in each data storage area, the at least one preference value operable by the client station between a first position and a second position for indicating a predetermined processing preference of the client station.

8. The system according to claim 7 comprising a second different storage location for storing a second different status indicator value within each data storage area, the second different status indicator value operable by the processor array between a first position and a second position for indicating that the processing of data within the data storage area is complete.

9. A method for allocating resources of an encryption processor the method comprising:

writing an independent block of subsequent data to a first data storage area from a first client station;

setting a first status indicator value in the first data storage area by providing a value from the client station for indicating that the subsequent data in the first data storage area is ready for processing;

checking the first status indicator value in the first data storage area immediately before the processor is finished processing an independent block of current data in a second data storage area, to determine a set value thereof;

connecting a serial encryption processor to the first data storage area for processing the subsequent data therein immediately after the encryption processor has completed processing the current data in the second data storage area, absent communication external to the encryption processor and in dependence upon the first status indicator value in the first data storage area being set to a value indicative of a ready status;

writing processed data from the encryption processor to the first data storage area;

setting a second status indicator value in the first data storage area by providing a value from the encryption processor, the second status indicator value indicative of processed data therein; and

the setting, checking, and connecting resulting in successive switching between a first mode and a second mode by the processor array, such that in a first mode the first data storage area is available to the encryption processor and the second data storage area is available to a client station, and in the second mode the first data storage area is available to a client station and the second data storage area is available to the encryption processor.

10. The method according to claim 9 wherein the encryption processor is coupled to the status indicator value in the first data storage area via gating logic.

11. The method according to claim 10 wherein the gating logic provides a signal to the encryption processor indicative of a next data storage area having data that is ready for immediate processing thereof.

12. The method according to claim 9 wherein the encryption processor polls the status indicator value in the first data storage area to determine a set value thereof.

13. The method according to claim 12 comprising, prior to the step of setting a first status indicator value, the step of:

setting at least a separate preference value in the first data storage area by providing a value from the client station for indicating at least a processing preference of the client station.