Memory device having error checking and correction

• US 7,386,765 B2
• Filed: 09/29/2003
• Issued: 06/10/2008
• Est. Priority Date: 09/29/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bains, Kuljit S., Ellis, Robert M., Freeman, Chris B., Halbert, John B.
• Primary Examiner(s): Chen; Alan S.
• Application Number:
  US10/674,320
• Publication Number:
  US 20050081085A1
• Time in Patent Office: 1,716 Days
• Field of Search: 710/6, 710/7, 710/58, 710/59, 710/60, 710/18, 714/6, 714/42
• US Class Current: 714/42
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution

Abstract

Apparatus and method to carry out checks for memory errors within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.

Claims

1. A memory device comprising:

a storage array comprised of a plurality of memory cells;

an interface buffer coupled to the storage array, and having a first interface to couple the memory device to a first memory bus to couple the memory device to a memory controller;

memory error logic associated with the interface buffer to carry out a check for memory errors within the storage array under at least one of conditions comprising in response to a command from the memory controller and during an idle period associated with transactions carried out by the memory controller on the first memory bus that involve the storage array; and

bus error logic associated with the interface buffer to carry out a check for bus errors in transactions across the first memory bus between the memory controller and the first interface.

2. The memory device of claim 1, wherein the memory error logic is a component of the interface buffer, and wherein the memory device is comprised of a circuitboard to which is attached at least one integrated circuit that comprises the storage array and at least one integrated circuit that comprises the interface buffer.

3. The memory system device of claim 1, wherein, the first memory bus provides a point-to-point connection between the memory device and the memory controller, the interface buffer has a second interface to couple the memory device to a second memory bus to provide a point-to-point connection between the memory device and another memory device, and the interface buffer passes through bus activity between the first and second memory busses that does not involve the storage array.

4. The memory device of claim 3, wherein both a transfer of data between the memory controller and the first interface of the interface buffer and a transfer of data between the second interface of the interface buffer and the another memory device occur with data transmitted in a packets.

5. The memory device of claim 3, wherein the memory error logic corrects a memory error, if a memory error is detected and is correctable;

and the memory error logic transmits a signal to the memory controller if a memory error is detected and is not correctable.

6. The memory device of claim 1, wherein a transaction across the first memory bus entails the transmission of data in a packet with CRC information, and the bus error logic examines the data and the CRC information to check for an occurrence of a bus error.

8. The memory device of claim 1, wherein during the idle period, there are no transactions carried out by the memory controller on the first memory bus that involve the storage array.

7. A computer system comprising:

a processor;

a disk storage device coupled to the processor

a memory controller coupled to the processor;

a first memory bus coupled to the memory controller;

a first memory device having a first storage array comprised of a plurality of memory cells and a first interface buffer coupled within the first memory device to the first storage array, wherein the first interface buffer provides a first interface by which the first memory device is coupled to the first memory bus forming a point-to-point connection between the memory controller and the first interface, a first memory error logic to carry out a check for memory errors within the first storage array under at least one of conditions comprising in response to a first command from the memory controller and during an idle period associated with transactions carried out by the memory controller on the first memory bus that involve the first storage array, and a first bus error logic associated with the first interface buffer to carry out a check for bus errors in transactions on the first memory bus between the memory controller and the first interface.

9. The computer system of claim 7, wherein during the idle period, there are no transactions carried out by the memory controller on the first memory bus that involve the first storage array.

10. The computer system of claim 7, wherein the first interface buffer further comprises a second interface.

11. The computer system of claim 10, further comprising:

a second memory bus coupled to the second interface; and

a second memory device having a second storage array comprised of a plurality of memory cells and a second interface buffer coupled within the second memory device to the second storage array, wherein the second interface buffer provides a third interface by which the second memory device is coupled to the second memory bus forming a point-to-point connection between the third interface and the second interface, a second memory error logic to carry out a check for memory errors within the second storage array under at least one of conditions comprising in response to a second command from the memory controller and during an idle period associated with transactions carried out by the memory controller on the second memory bus that involve the second storage array, and a second bus error logic associated with the second interface buffer to carry out a check for bus errors in transactions across the second memory bus between the memory controller and the second interface.

12. The computer system of claim 11, wherein during the idle period, there are no transactions carried out by the memory controller on the second memory bus that involve the second storage array.