Programmable bit error rate monitor for serial interface

• US 7,386,767 B1
• Filed: 10/05/2004
• Issued: 06/10/2008
• Est. Priority Date: 10/05/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Xue, Ning, Lee, Chong H
• Primary Examiner(s): Trimmings; John P
• Application Number:
  US10/958,447
• Time in Patent Office: 1,344 Days
• Field of Search: 714/704
• US Class Current: 714/704
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers

Abstract

A programmable bit error rate monitor includes an error counter, a monitoring period counter with a programmable upper bound to set the monitoring period, and an error flag generator that compares the actual error count to a programmable threshold. The error flag generator may generate flags at different sensitivity levels, and the user may programmably select one of those flags. The three flags can be generated by independent comparators, or they can be extrapolated from the base error flag—e.g., by comparing only certain bits of the error count to corresponding bits of the threshold.

Claims

1. A programmable bit error rate monitor for a serial data interface, said monitor comprising:

a bit error counter adapted to receive a serial data stream and to output a count of errors in said serial data stream;

a monitoring period counter adapted to receive (a) a clock associated with said serial data stream and (b) user input of a monitoring period duration, and to generate a monitoring period detection signal upon passage of said monitoring period duration; and

an error flag generator adapted to receive (1) user input of an error threshold, (2) said monitoring period detection signal, and (3) said count of errors from said bit error counter, and to output, in parallel, a plurality of error flags at different error resolutions, including a base error flag, when, within any said monitoring period duration, said count of errors exceeds said error threshold.

2. The programmable bit error rate monitor of claim 1 wherein said monitoring period detection signal is output to said bit error counter as a reset signal for said bit error counter.

3. The programmable bit error rate monitor of claim 1 further comprising a multiplexer having as inputs (a) said plurality of error flags and (b) a user signal selecting one of said plurality of error flags.

4. The programmable bit error rate monitor of claim 1 wherein said plurality of error flags comprises said base error flag and at least one additional error flag extrapolated from said base error flag.

5. The programmable bit error rate monitor of claim 4 wherein said error flag generator extrapolates said at least one additional error flag by comparing a range of bits of said count of errors of a predetermined significance to a range of bits of said threshold of said predetermined significance.

6. The programmable bit error rate monitor of claim 5 wherein:

said error flag generator generates said base error flag and first and second additional error flags;

said error flag generator generates said base error flag by comparing all bits of said count of errors to all bits of said threshold;

said error flag generator generates said first additional error flag by comparing all but a group of least significant bits of said count of errors to all but a group of most significant bits of said threshold; and

said error flag generator generates said first second additional error flag by comparing only a group of most significant bits of said count of errors to only a group of least significant bits of said threshold.

7. The programmable bit error rate monitor of claim 4 wherein:

said error flag generator generates said base error flag and first and second additional error flags.

8. The programmable bit error rate monitor of claim 1 wherein:

said error flag generator generates said base error flag and first and second additional error flags.

9. A programmable logic device comprising a programmable bit error rate monitor according to claim 1.

10. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

a programmable logic device as defined in claim 9 coupled to the processing circuitry and the memory.

11. A printed circuit board on which is mounted a programmable logic device as defined in claim 9.

12. The printed circuit board defined in claim 11 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

13. The printed circuit board defined in claim 12 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.