Memory channel with bit lane fail-over

• US 7,386,768 B2
• Filed: 06/05/2003
• Issued: 06/10/2008
• Est. Priority Date: 06/05/2003
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Brzezinski, Dennis W., Morrow, Warren R., Vogt, Pete D.
• Primary Examiner(s): Trimmings; John P
• Application Number:
  US10/456,353
• Publication Number:
  US 20040250181A1
• Time in Patent Office: 1,832 Days
• Field of Search: None
• US Class Current: 714/710
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4256 using a clocked protocol
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Claims

1. A memory buffer comprising:

an inbound redrive circuit to receive and redrive signals on an inbound path, the inbound redrive circuit having a plurality of input/output (I/O) cells, each I/O cell providing, at least in part, a bit-lane for a unidirectional point-to-point channel between a first memory agent and a second memory agent

a failover circuit coupled with the inbound redrive circuit, the failover circuit capable of redirecting a signal from a first bit-lane of the unidirectional point-to-point channel to a second bit-lane of the unidirectional point-to-point channel;

an outbound redrive circuit to receive and redrive signals on an outbound path;

a memory interface to couple the memory buffer to a plurality of memory devices, the memory interface to receive data from the outbound redrive circuit and to send data to the inbound redrive circuit; and

deskew logic coupled between the outbound redrive circuit and the memory interface to reduce skew between bits of data received from the outbound redrive circuit,

wherein the memory buffer is capable of selectively disabling the outbound redrive circuit if it is the last agent on the channel.

2. The memory buffer of claim 1, wherein the failover circuit includes a plurality of switches, each switch coupled between two bit-lanes of the unidirectional point-to-point channel and capable of selectively providing the signal to one of the two bit-lanes.

3. The memory buffer of claim 1, further comprising:

a memory interface to provide an interface between the memory buffer and one or more dynamic random access memory devices.

4. The memory buffer of claim 1, wherein the failover circuit is integrated with the redrive circuit.