Translation of high-level circuit design blocks into hardware description language

• US 7,386,814 B1
• Filed: 02/10/2005
• Issued: 06/10/2008
• Est. Priority Date: 02/10/2005
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Kelly, Sean A., Stroomer, Jeffrey D., Milne, Roger B., Foraker, Isaac W.
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): LEVIN, NAUM B
• Application Number:
  US11/054,864
• Time in Patent Office: 1,216 Days
• Field of Search: 716 2- 3, 703 14- 16
• US Class Current: 716/103
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

Translation of high-level design blocks into a design specification in a hardware description language (HDL). Each block in the high-level design is assigned to a group. A set of attributes is identical between the blocks in a group. For each group of blocks, a respective set of parameters having different values on subblocks of at least two blocks in the group is determined. An HDL specification is generated for each group. The HDL specification for a group has for each parameter in the set of parameters, a parameter input.

Claims

1. A method for translating high-level design blocks into a design specification in a hardware description language (HDL), wherein each of a plurality of the high-level design blocks has one or more parameters, each parameter having an associated parameter value, the method comprising:

assigning each of the high-level design blocks to a group, wherein a set of attributes is identical between each high-level design block in a group;

determining for each group of the high-level design blocks, a respective set of parameters that for each parameter in the set has different values in at least two high-level design blocks in the group; and

generating a respective HDL specification for each group, the HDL specification having for each parameter in the set of parameters, a respective parameter input,

wherein the generating of the respective HDL specification includes;

generating an HDL specification of a first high-level design block having a respective parameter for each parameter in the set of Parameters, and assigning each respective parameter to a variable in the HDL specification of the first high-level design block; and

generating for each high-level design block in the group, an HDL specification of a respective entity of a type of the first high-level design block, and providing in each respective entity the associated parameter value from the respective high-level design block for each respective parameter.

2. The method of claim 1, wherein assigning each of the high-level design blocks to a group includes sorting the high-level design blocks by values of the set of attributes.

3. The method of claim 1, wherein assigning each of the high-level design blocks to a group includes applying a hash function to data describing each high-level design block.

4. The method of claim 1, wherein the set of attributes include names of blocks, types of blocks, directions of ports on blocks, numbers of subblocks, instance names of blocks, HDL entity name used to implement each subblock, names of parameters used on each subblock, and connections between subblocks.

5. The method of claim 4, wherein generating an HDL specification comprises:

making a copy of a block in a group;

for the respective set of parameters of the group having different values, replacing in the copy of the block each value assigned to a parameter with a name assigned to the parameter; and

generating the HDL specification from the copy of the block.

6. The method of claim 5, further comprising, for each high-level design block in a group, generating HDL code that declares the each high-level design block as an instance of the HDL specification of the group using parameter values of the each high-level design blocks.

7. A system for translating high-level design blocks into a design specification in a hardware description language (HDL), wherein each of a plurality of the high-level design blocks has one or more parameters, each parameter having an associated parameter value, the system comprising:

means for assigning each of the high-level design blocks to a group, wherein a set of attributes is identical between each high-level design block in a group;

means for determining for each group of the high-level design blocks, a respective set of parameters that for each parameter in the set has different values in at least two high-level design blocks in the group; and

means for generating a respective HDL specification for each group, the HDL specification having for each parameter in the set of parameters, a respective parameter input,

wherein the means for generating a respective HDL specification includes;

means for generating an HDL specification of a first high-level design block having a respective parameter for each parameter in the set of parameters, and assigning each respective parameter to a variable in the HDL specification of the first high-level design block; and

means for generating for each high-level design block in the group, an HDL specification of a respective entity of a type of the first high-level design block, and providing in each respective entity the associated parameter value from the respective high-level design block for each respective parameter.