Packaging of electronic chips with air-bridge structures

• US 7,387,912 B2
• Filed: 08/31/2005
• Issued: 06/17/2008
• Est. Priority Date: 08/25/1999
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farrar, Paul A.
• Primary Examiner(s): Graybill; David E
• Application Number:
  US11/216,486
• Publication Number:
  US 20050285220A1
• Time in Patent Office: 1,021 Days
• Field of Search: None
• US Class Current: 438/115
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 23/20 gaseous at the normal operating temperature of the device
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/4821 Bridge structure with air gap
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structure embedded in a plurality of materials having a plurality of vaporization temperatures. The plurality of materials is formed on the electronic chip and the conductive structure is coupled to the electronic chip. To fabricate the circuit assembly, a support structure, including interstices, is formed on an electronic chip. The interstices of the support structure are filled with a material having a vaporization temperature that is less than the vaporization temperature of the support structure. Conductive structures are embedded in the support structure and the material, and a connective structure is mounted on the support structure. Finally, the material is removed from the interstices by heating the circuit assembly.

Claims

1. A method comprising:

fabricating a plurality of electronic devices on a substrate;

embedding a wiring structure in a plurality of materials having a plurality of vaporization temperatures, the plurality of materials is located on the substrate and the wiring structure interconnects the plurality of electronic devices;

mounting an integrated circuit on a packaging substrate; and

removing at least one of the plurality of materials after the integrated circuit is mounted on the packaging substrate.

2. The method of claim 1, further comprising:

attaching a C4 structure to the integrated circuit prior to mounting the integrated circuit on the packaging substrate.

3. The method of claim 2, wherein removing at least one of the plurality of materials after the integrated circuit is mounted on the packaging substrate comprises:

heating the integrated circuit.

4. The method of claim 3, wherein heating the integrated circuit comprises:

placing the integrated circuit in a furnace having an oxygen atmosphere heated to about 400 degrees centigrade.

15. The method of claim 1, wherein the plurality of materials includes a fill material.

16. The method of claim 15, wherein the fill material includes carbon.

17. The method of claim 1, wherein the plurality of materials includes a support structure.

18. The method of claim 17, wherein the support structure includes SiO₂.

5. A method comprising:

forming an air bridge structure including;

forming a support structure having a support structure vaporization temperature and having interstices on an electronic chip;

filling the interstices of the support structure with a fill material having a vaporization temperature that is less than the support structure vaporization temperature;

embedding a conductive structure in the support structure and the fill material, wherein embedding the conductive structure includes forming the conductive structure having a horizontal conductive interconnect and at least one vertical wiring via coupling the horizontal conductive interconnect to the electronic chip, and wherein the horizontal conductive interconnect is formed in contact with and above the fill material;

mounting a connective structure on the support structure; and

removing the fill material.

6. The method of claim 5, wherein forming a support structure having a support structure vaporization temperature and having interstices on an electronic chip comprises:

depositing a layer of silicon dioxide on the electronic chip; and

etching the layer of silicon dioxide to form the support structure having interstices.

19. The method of claim 5, wherein the support structure includes SiO₂.

20. The method of claim 5, wherein the fill material includes carbon.

7. A method comprising:

forming an air bridge structure including;

forming a support structure having interstices on an electronic chip;

filling the interstices of the support structure with a fill material having a vaporization temperature that is less than the vaporization temperature of the support structure;

embedding a conductive structure in the fill material, wherein embedding the conductive structure includes forming the conductive structure having a horizontal conductive interconnect and at least one vertical wiring via coupling the horizontal conductive interconnect to the electronic chip, and wherein the horizontal conductive interconnect is formed in contact with and above the fill material;

mounting a connective structure on the support structure; and

vaporizing the fill material.

8. The method of claim 7, wherein filling the interstices of the support structure with a fill material having a vaporization temperature that is less than the vaporization temperature of the support structure comprises:

depositing a layer of carbon on the electronic chip.

9. The method of claim 8, wherein depositing a layer of carbon on the electronic chip comprises:

sputtering the layer of carbon on the electronic chip.

10. The method of claim 9, further comprising:

planarizing the layer of carbon.

21. The method of claim 7, wherein the support structure includes SiO₂.

11. A method comprising:

fabricating an integrated circuit structure including a conductive structure and a ribbed support structure embedded in a fill material;

mounting controlled collapse chip connection pads on the integrated circuit structure;

mounting the integrated circuit structure on a substrate;

removing the fill material; and

backfilling with a gas and hermetically sealing the substrate.

12. The method of claim 11, wherein the gas is helium.

13. The method of claim 11, wherein the fill material is carbon.

14. The method of claim 11, wherein the structural material is SiO₂.

22. A method comprising:

forming a material layer on a surface of an electronic chip including a plurality of devices, the material layer having a non-conductive ribbed structure having a depth and forming at least one interstice;

forming within the material layer a plurality of conductive segments including at least one air-bridge structure having a horizontal conductive interconnect within the material layer and above and not in contact with the surface of the electronic chip,

forming at least one vertical wiring via coupling the horizontal conductive interconnect to one or more of the plurality of electronic devices;

forming a controlled collapse chip connection (C4) structure including an insulating layer formed above the ribbed structure, above the conductive segments, and above the interstices, and coupled to the electronic chip through a plurality of conductive elements coupled to one or more of the plurality of conductive segments; and

a substrate coupled to the C4 structure.

23. The method of claim 22, further including:

hermetically sealing the at least one interstice.

24. The method claim 23, wherein hermetically sealing the at least one interstice includes:

back filling the at least one interstice with helium.

25. The method claim 23, wherein hermetically sealing the at least one interstice includes:

back filling the at least one interstice with a helium rich gas mixture.

26. The method claim 22, further including:

coupling a heat sink to the substrate.