Structure for determining thermal cycle reliability

• US 7,388,224 B2
• Filed: 08/10/2006
• Issued: 06/17/2008
• Est. Priority Date: 02/20/2004
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: McLaughlin, Paul Stephen, Gill, Jason Paul, Wang, Ping-Chuan, Murray, Conal Eugene, Shaw, Thomas M., McGahay, Vincent J., Filippi, Ronald Gene, Rathore, Hazara Singh
• Primary Examiner(s): Baumeister; Bradley W.
• Assistant Examiner(s): Fulk; Steven J
• Application Number:
  US11/502,196
• Publication Number:
  US 20060273460A1
• Time in Patent Office: 677 Days
• Field of Search: 257/48, 257/E23.145, 438/18, 438/638
• US Class Current: 257/48
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/0268 for electrical inspection or testing
• CPC Class Codes: H05K 1/0269 for visual or optical inspection
• CPC Class Codes: H05K 1/092 Dispersed materials, e.g. conductive pastes or inks
• CPC Class Codes: Y10S 438/927 Electromigration resistant metallization
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part

Abstract

A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

Claims

1. A test structure used to determine reliability performance of a semiconductor chip structure, comprising:

a patterned metallization structure having a plurality of interfaces, which provide stress risers, the metallization structure including at least one of;

a via chain formed through layers of the semiconductor chip structure such that a plurality of widths of vias are used to adjust strain in different layers, and

a dummy structure formed to provide a via density in an area of the semiconductor chip structure to adjust strain in adjacent structures of the test structure; and

a dielectric material surrounding the metallization structure, where a mismatch in coefficients of thermal expansion (CTE) between the metallization structure and the surrounding dielectric material exist, wherein the mismatch in CTE between the metallization structure and the dielectric material is greater than about 20 ppm/°

C. such that the test structure includes a thermal strain value to cause failures under given stress conditions as a result of CTE mismatch to provide a yield indicative of reliability for a manufacturing design.

2. The structure as recited in claim 1, wherein the same strain value is across vias in the test structure.

3. The structure as recited in claim 1, wherein the patterned metallization structure includes a dual damascene structure.

4. The structure as recited in claim 3, further comprising conductive liners along bottoms and sidewalls of vias in the dual damascene structure.

5. The structure as recited in claim 4, wherein the liners include one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN) and tungsten (W).

6. The structure as recited in claim 1, wherein the metallization structure includes one of aluminum (Al), copper (Cu), Gold (Au), silver (Ag) and alloys thereof.

7. The structure as recited in claim 1, wherein the dielectric material includes an organic material.

8. The structure as recited in claim 1, wherein the dielectric material includes one of a resin, polyamide, SiCOH, a nitride and an oxide.

9. The structure as recited in claim 1, wherein the metallization structure includes a stacked via chain having at least two levels of interconnects and vias.

10. The structure as recited in claim 1, farther comprising dummy structures not electrically connected to the metallization structure and placed near ends of the test structure to reduce the variation in thermal strain at corner or end vias.

11. The structure as recited in claim 1, wherein the metallization structure is separated from metal pads by a distance to reduce thermal expansion effects caused by the metal pads.

12. The structure as recited in claim 11, wherein the distance between the metallization structure and the metal pads is such that a reduction in thermal strain of any via is within 5% of a maximum value of thermal strain that exists between the metallization structure and the dielectric material for a completely isolated via.

13. The structure as recited in claim 1, wherein the metallization structure further comprises multiple sections electrically connected and separated by a distance to reduce thermal expansion effects caused by adjacent vias.

14. The structure as recited in claim 13, wherein the distance between the sections is such that a reduction in thermal strain of any section is within 5% of a maximum value of thermal strain that exists between the metallization structure and the dielectric material for a completely isolated section of vias.