Trench metal-insulator-metal (MIM) capacitors and method of fabricating same

• US 7,388,244 B2
• Filed: 09/22/2005
• Issued: 06/17/2008
• Est. Priority Date: 09/22/2005
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Ho, Herbert L., Iyer, Subramanian S., Ramachandran, Vidhya
• Primary Examiner(s): Whitehead, Jr.; Carl
• Assistant Examiner(s): Harrison; Monica D
• Application Number:
  US11/162,776
• Publication Number:
  US 20070063244A1
• Time in Patent Office: 999 Days
• Field of Search: 438/386, 438/246, 438/243, 257/68, 257/301
• US Class Current: 257/301
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 12/0387 Making the trench

Abstract

The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET). The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap. The semiconductor device of the present invention can be fabricated by a process in which the trench MIM capacitor is formed after the FET source/drain region but before the FET source/drain metal silicide contacts, for minimizing metal contamination in the FET.

Claims

1. A semiconductor device, comprising:

at least one trench capacitor that comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in said trench over the first metallic electrode layer, and a second metallic electrode layer located in said trench over the dielectric layer; and

at least one field effect transistor (FET) located on said substrate, said at least one FET comprising a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region,

wherein the second metallic electrode layer of the trench capacitor is electrically connected to at least one of the source and drain regions of the at least one FET by a metallic region including a metal silicide strap and a non-silicided metal, said non-silicided metal forms a direct contact between the second metallic electrode layer and the metal silicide strap.

2. The semiconductor device of claim 1, wherein said first and second metallic electrode layers of the trench capacitor comprise at least one metal, metal alloy, metal nitride, or metal silicide.

3. The semiconductor device of claim 1, wherein said first and second metallic electrode layers of the trench capacitor comprise metallic material(s) selected from the group consisting of Ti, TiN, W, WN, Ru, and combinations thereof.

4. The semiconductor device of claim 1, wherein the substrate comprises a semiconductor-on-insulator structure.

5. The semiconductor device of claim 1, wherein the substrate comprises a bulk semiconductor structure.

6. The semiconductor device of claim 5, wherein the trench has sidewalls with p-type implants.

7. The semiconductor device of claim 5, wherein the trench is located in a p-well in the substrate.

8. The semiconductor device of claim 1, wherein the source and drain regions of the at least one FET comprises a metal silicide contact layer.

9. The semiconductor device of claim 8, wherein the trench capacitor further comprises a metal silicide layer located between the first metallic electrode layer and the interior walls of the trench in the substrate.

10. A method for forming a semiconductor device, comprising:

forming at least one field effect transistor (FET) on a substrate, wherein said at least one FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region;

forming a capacitor trench in said substrate;

forming a first metallic electrode layer over interior walls of the capacitor trench;

forming a dielectric layer in said trench over the first metallic electrode layer;

forming a second metallic electrode layer in said trench over the dielectric layer; and

forming a metal silicide contact layer in the source and drain regions of the at least one FET and a metallic region including a metal silicide strap and a non-silicided metal between the at least one FET and the trench capacitor, wherein the metal silicide strap electrically connects the second metallic electrode layer of the trench capacitor and at least one of the source and drain regions of the at least one FET and said non-silicided metal forms a direct contact between the second metallic electrode layer and the metal silicide strap.

11. The method of claim 10, wherein said first and second metallic electrode layers of the trench capacitor comprise at least one metal, metal alloy, metal nitride, or metal silicide.

12. The method of claim 10, wherein the substrate comprises a semiconductor-on-insulator structure.

13. The method of claim 10, wherein the substrate comprises a bulk semiconductor structure, and wherein the trench either has sidewalls with p-type implants or is located in a p-well in the substrate.

14. The method of claim 10, wherein the metal silicide contact layer and the metal silicide strap are formed by:

depositing a metal layer over the substrate to cover the at least one FET and the trench capacitor;

annealing the metal layer at an elevated temperature to form the metal silicide contact layer in the source and drain regions of the at least one FET and the metal silicide strap between the at least one FET and the trench capacitor; and

removing unreacted metal from surface of the substrate.

15. The method of claim 14, wherein during the annealing, a metal silicide layer is formed between the first metallic electrode layer and the interior walls of the trench in the substrate.