Metal-insulator varactor devices

• US 7,388,276 B2
• Filed: 07/07/2005
• Issued: 06/17/2008
• Est. Priority Date: 05/21/2001
• Status: Expired due to Fees

• Current Assignee: The Board of Regents of the University of Colorado (University of Colorado System)
• Original Assignee: The Board of Regents of the University of Colorado (University of Colorado System)
• Inventors: Estes, Michael J.
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US11/176,404
• Publication Number:
  US 20060267150A1
• Time in Patent Office: 1,076 Days
• Field of Search: 257/595, 257/598, 257/E29.344, 257/600, 257/E27.049, 438/379
• US Class Current: 257/595
• CPC Class Codes: H01G 7/06 having a dielectric selected for the variation of its permittivity with applied voltage, i.e. ferroelectric capacitors electrets H01G7/02
• CPC Class Codes: H01L 27/0811 MIS diodes

Abstract

A varactor is configured with first and second conducting layers, spaced apart from one another such that a given voltage can be applied across the first and second conducting layers. Further, an insulator arrangement includes at least one insulator layer disposed between the first and second conducting layers, configured to cooperate with the first and second conducting layers to produce a charge pool which changes responsive to changes in the given voltage such that a device capacitance value between the first and second conducting layers changes responsive to the given voltage. The insulator arrangement can include one layer, two distinct layers or more than two distinct layers. One or more of the layers can be an amorphous material. A zero-bias voltage version of the varactor is also described.

Claims

1. A varactor, comprising:

first and second conducting layers, spaced apart from one another such that a given voltage can be applied across the first and second conducting layers; and

an insulator arrangement including at least one insulator layer disposed between the first and second conducting layers, configured to cooperate with the first and second conducting layers to produce a charge pool within said insulator layer which changes responsive to changes in said given voltage such that a device capacitance value between the first and second conducting layers changes responsive to said given voltage.

2. The varactor of claim 1 wherein said insulator arrangement is configured such that increasingly biasing the first conducting layer more positive than the second conducting layer, using said given voltage, produces a corresponding increase in said device capacitance value.

3. The varactor of claim 1 wherein said insulator arrangement includes at least a first insulator layer, adjacent to said first conducting layer, and a second insulator layer, adjacent to said second conducting layer and in a side-by-side relationship with said first insulator layer so as to define a boundary therebetween for producing said charge pool in the second one of said insulator layers proximate to said boundary with the first one of the insulator layers.

4. The varactor of claim 3 wherein said first insulator layer includes a first barrier height and said second insulator layer includes a second barrier height, and the first and second barrier heights are selected to produce tunneling of electrons from said second conducting layer through said second insulator layer, responsive to the given voltage, and to inhibit tunneling of electrons across said first insulator layer to generate said charge pool.

5. The varactor of claim 4 wherein said first barrier height is greater than said second barrier height.

6. The varactor of claim 5 wherein said first barrier height is much greater than 1 eV and said second barrier height is less than 0.3 eV.

7. The varactor of claim 3 wherein said first insulator layer includes a first capacitance value and said second insulator layer includes a second capacitance value such that an application of said given voltage which causes the first conducting layer to be increasingly negative with respect to the second conducting layer, below a given threshold value of said given voltage, causes said device capacitance value to approach a series combination of said first capacitance value and said second capacitance value and application of said given voltage which causes the first conducting layer to be increasingly positive with respect to the second conducting layer, above said given threshold value of said given voltage, causes said device capacitance value to approach said first capacitance value of the first insulator layer.

8. The varactor of claim 7 wherein said varactor is configured in a way which sets said threshold value of said given voltage, at least approximately, to zero volts.

9. The varactor of claim 1 wherein said insulator arrangement includes only one layer of an insulation material between said first and second conducting layers and said insulation material includes an insulator barrier height that cooperates with a second layer work function of said second conducting layer to produce a negative barrier height between the insulation material and the second conducting layer, responsive to said given voltage, such that the charge pool is formed in said insulator material proximate to a boundary with the second conducting layer.

10. The varactor of claim 9 wherein said charge pool includes a width that is modulated by changes in said given voltage.

11. The varactor of claim 1 wherein said insulator arrangement includes at least one layer of an amorphous material.

12. The varactor of claim 1 wherein said insulator arrangement is configured to cooperate with said first and second conducting layers to support electron tunneling, responsive to said given voltage, which produces said charge pool within the insulator arrangement, said charge pool storing an amount of charge in the insulator arrangement that changes based on said electron tunneling such that said device capacitance value between the first and second conducting layers changes responsive to said given voltage.