Top layers of metal for high performance IC's
First Claim
Patent Images
1. An integrated circuit chip comprising:
- a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, a second opening in said passivation layer exposing a second pad of said first metallization structure, and a third opening in said passivation layer exposing a third pad of said first metallization structure, wherein said first, second and third pads are separate from one another, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip;
a second metallization structure over said passivation layer and over said first, second and third pads, wherein said second metallization structure comprises electroplated copper, wherein said second metallization structure comprises a third metal layer and a fourth metal layer over said third metal layer, said third metal layer having a thickness greater than those of said first and second metal layers, and said fourth metal layer having a thickness greater than those of said first and second metal layers, and wherein said first pad is connected to said second and third pads through a clock distribution network of said second metallization structure, and said second pad is connected to said third pad through said clock distribution network; and
a first polymer layer between said third and fourth metal layers, wherein said first polymer layer has a thickness greater than those of said passivation layer, said first dielectric layer and said second dielectric layer.
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Abstract
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
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Citations
21 Claims
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1. An integrated circuit chip comprising:
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a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, a second opening in said passivation layer exposing a second pad of said first metallization structure, and a third opening in said passivation layer exposing a third pad of said first metallization structure, wherein said first, second and third pads are separate from one another, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; a second metallization structure over said passivation layer and over said first, second and third pads, wherein said second metallization structure comprises electroplated copper, wherein said second metallization structure comprises a third metal layer and a fourth metal layer over said third metal layer, said third metal layer having a thickness greater than those of said first and second metal layers, and said fourth metal layer having a thickness greater than those of said first and second metal layers, and wherein said first pad is connected to said second and third pads through a clock distribution network of said second metallization structure, and said second pad is connected to said third pad through said clock distribution network; and a first polymer layer between said third and fourth metal layers, wherein said first polymer layer has a thickness greater than those of said passivation layer, said first dielectric layer and said second dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An integrated circuit chip comprising:
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a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper; a second dielectric layer between said first and second metal layers; an inorganic layer over said first and second dielectric layers; a first polymer layer over said inorganic layer, a first opening in said first polymer layer exposing a first pad of said first metallization structure, a second opening in said first polymer layer exposing a second pad of said first metallization structure, and a third opening in said first polymer layer exposing a third pad of said first metallization structure, wherein said first, second and third pads are separate from one another, wherein said first polymer layer has a thickness between 2 micrometers and 30 micrometers and greater than those of said inorganic layer, said first dielectric layer and said second dielectric layer; and a second metallization structure over said first polymer layer and over said first, second and third pads, wherein said second metallization structure comprises electroplated copper, wherein said second metallization structure comprises a third metal layer, with a thickness greater than those of said first and second metal layers, and a fourth metal layer, with a thickness greater than those of said first and second metal layers, over said third metal layer, and wherein said first pad is connected to said second and third pads through a clock distribution network of said second metallization structure, and said second pad is connected to said third pad through said clock distribution network; and a second polymer layer between said third and fourth metal layers, wherein said second polymer layer has a thickness greater than those of said inorganic layer, said first dielectric layer and said second dielectric layer. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. An integrated circuit chip comprising:
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a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises aluminum; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, a second opening in said passivation layer exposing a second pad of said first metallization structure, and a third opening in said passivation layer exposing a third pad of said first metallization structure, wherein said first, second and third pads are separate from one another, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip, wherein said topmost nitride layer is over said topmost oxide layer; a second metallization structure over said passivation layer and over said first, second and third pads, wherein said second metallization structure comprises electroplated copper, wherein said second metallization structure comprises a third metal layer, with a thickness greater than those of said first and second metal layers, and a fourth metal layer, with a thickness greater than those of said first and second metal layers, over said third metal layer, and wherein said first pad is connected to said second and third pads through a clock distribution network of said second metallization structure, and said second pad is connected to said third pad through said clock distribution network; and a first polymer layer between said third and fourth metal layers, wherein said first polymer layer has a thickness greater than those of said passivation layer, said first dielectric layer and said second dielectric layer. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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Specification