Multiple level programming in a non-volatile device

• US 7,388,779 B2
• Filed: 06/16/2006
• Issued: 06/17/2008
• Est. Priority Date: 02/25/2005
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Nazarian, Hagop A.
• Primary Examiner(s): Hong; Huan
• Assistant Examiner(s): Graham; Kretelia
• Application Number:
  US11/454,737
• Publication Number:
  US 20060245257A1
• Time in Patent Office: 732 Days
• Field of Search: 365/185.03, 365/185.18
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

Abstract

The programming method of the present invention minimizes program disturb by initially programming cells on the same wordline with the logical state having the highest threshold voltage. The remaining cells on the wordline are programmed to their respective logical states in order of decreasing threshold voltage levels.

Claims

1. A method for programming a multiple level, non-volatile memory device, the method comprising:

applying a first series of incrementing programming voltage pulses to a wordline of the memory device to program a first set of memory cells of a plurality of memory cells, each memory cell having a plurality of programmable states wherein each state is represented by a threshold voltage distribution, a first maximum voltage of the first series of incrementing programming pulses being greater than remaining maximum programming voltages;

applying a second series of incrementing programming voltage pulses to the wordline to program a second set of memory cells, a second maximum voltage of the second series of incrementing programming voltage pulses being less than the first maximum voltage; and

programming remaining memory cells on the wordline in decreasing order of threshold voltage distribution.

2. The method of claim 1 wherein the non-volatile memory device is one of a NAND architecture flash memory device or a NOR architecture flash memory device.

3. The method of claim 1 wherein the first maximum voltage is for programming a first state and the second maximum voltage is for programming a second state.

4. The method of claim 1 wherein the first set of memory cells all have a first threshold voltage distribution and the second set of memory cells all have a second threshold voltage distribution.

5. The method of claim 4 wherein the first threshold voltage distribution is greater than the second threshold voltage distribution.