ADC architecture for wireless applications
First Claim
1. A method of concurrently converting a substantially orthogonal pair of analog signals having a predetermined nominal phase relationship into corresponding digital signals in a baseband processor, using only a single ADC (Analog to Digital Converter) circuit, the method comprising:
- providing a single ADC circuit;
during a first time interval, sampling a first one of the analog signals in the ADC circuit to provide a first digital signal;
during a second time interval non-overlapping the first time interval, sampling the other one of the pair of analog signals in the ADC circuit to provide a second digital signal; and
aligning the first and second digital signals so as to compensate for phase difference introduced by said sampling during the first and second time intervals, wherein said aligning comprises;
delaying a first one of the digital signals; and
interpolating the other one of the digital signals in a LPF (Low Pass Filter), so as to compensate for the phase difference introduced by said sampling during the first and second time intervals,wherein each of the first and second time intervals is equal to a predetermined ADC sample period corresponding to a sample clock cycle; and
said delaying the first digital signal comprises a delay of ½
clock cycle.
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Accused Products
Abstract
A simplified architecture is disclosed for ADC conversion of received in-phase I and quadrature Q signals. Circuit area is substantially reduced by sharing a single ADC to convert both signals, switching the ADC input alternately between the i and q signals. In an embodiment, the ADC is clocked at an increased sample rate, and the digital output signals are aligned to compensate for the phase difference resulting from the implementation of a single ADC. Aligning includes delaying one of the digital signals, and interpolating the other one of the digital signals in a low pass filter so as to compensate for the phase difference introduced by the sampling during the first and second time intervals. The first and second time intervals are equal to a predetermined ADC sample period corresponding to a sample clock cycle. Delaying the first digital signal includes a delay of 1/2 clock cycle.
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Citations
29 Claims
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1. A method of concurrently converting a substantially orthogonal pair of analog signals having a predetermined nominal phase relationship into corresponding digital signals in a baseband processor, using only a single ADC (Analog to Digital Converter) circuit, the method comprising:
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providing a single ADC circuit; during a first time interval, sampling a first one of the analog signals in the ADC circuit to provide a first digital signal; during a second time interval non-overlapping the first time interval, sampling the other one of the pair of analog signals in the ADC circuit to provide a second digital signal; and aligning the first and second digital signals so as to compensate for phase difference introduced by said sampling during the first and second time intervals, wherein said aligning comprises; delaying a first one of the digital signals; and interpolating the other one of the digital signals in a LPF (Low Pass Filter), so as to compensate for the phase difference introduced by said sampling during the first and second time intervals, wherein each of the first and second time intervals is equal to a predetermined ADC sample period corresponding to a sample clock cycle; and said delaying the first digital signal comprises a delay of ½
clock cycle. - View Dependent Claims (2, 3, 4)
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5. A baseband processor, comprising:
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a first input to receive a first analog signal encoding a first data stream; a second input to receive a second analog signal encoding a second data stream, the first and second analog signals having a predetermined phase relationship; a multiplexer responsive to the first and second inputs and arranged to select one at a time of the first and second analog signals; an ADC (Analog to Digital Converter) circuit to convert the selected analog signal so as to generate digital data; a demultiplexer circuit to steer the digital data generated by the ADC to a selected one of a first digital output and a second digital output, responsive to a demultiplexer control signal; and an alignment circuit to align a phase relation of the digital data provided by the demultiplexer at the first and second digital outputs such that the phase relation is substantially the same as said predetermined phase relationship of the first and second analog signals so as to compensate for phase difference introduced by said ADC circuit, wherein the ADC circuit converts the selected analog signal during one of first and second time intervals that are each equal to a predetermined ADC sample period corresponding to a sample clock cycle; and said compensating for the phase difference includes delaying the digital data for ½
clock cycle. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12)
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13. A wireless transceiver, comprising:
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a transmitter circuit to encode and transmit data modulated onto at least one selected RF (radio frequency) band; and a receiver circuit to receive signals on the selected RF band, demodulate the received signals to form a pair of baseband analog signals and recover the transmitted data from the baseband signals; the receiver circuit including a baseband processor to convert the baseband analog signals into digital output vector streams, wherein the baseband processor comprises a single ADC (Analog to Digital Converter) circuit arranged to alternately sample the baseband analog signals to form the digital output vector streams and a phase adjustment circuit to align the first and second digital output vector streams so as to compensate for a phase difference introduced by said alternately sampling the baseband analog signals to form the digital output vector streams, wherein the ADC circuit alternately samples the baseband analog signals during first and second time intervals that are each equal to a predetermined ADC sample period corresponding to a sample clock cycle; and said compensating for the phase difference includes delaying one of the first and second digital output vector streams for ½
clock cycle. - View Dependent Claims (14)
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15. A network interface apparatus, comprising:
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a network interface; and a wireless transceiver responsive to said network interface, said wireless transceiver comprising; a transmitter circuit to encode and transmit data modulated onto at least one selected RF (radio frequency) band; and a receiver circuit to receive signals on the selected RF band, demodulate the received signals to form a pair of baseband analog signals and recover the transmitted data from the baseband signals; the receiver circuit including a baseband processor to convert the baseband analog signals into digital output vector streams, wherein the baseband processor comprises a single ADC (Analog to Digital Converter) circuit arranged to alternately sample the baseband analog signals to form the digital output vector streams; and an alignment circuit to align a phase relation of the digital output vector streams so as to compensate for phase difference introduced by said single ADC circuit, wherein the ADC circuit alternately samples the baseband analog signals during first and second time intervals that are each equal to a predetermined ADC sample period corresponding to a sample clock cycle; and said compensating for the phase difference includes delaying one of the digital output vector streams for ½
clock cycle.
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16. An information processing apparatus, comprising:
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an information processor; and a network interface apparatus responsive to said processor, the network interface apparatus comprising; a network interface; and a wireless transceiver responsive to said network interface, said wireless transceiver comprising; a transmitter circuit to encode and transmit data modulated onto at least one selected RF (radio frequency) band; and a receiver circuit to receive signals on the selected RF band, demodulate the received signals to form a pair of baseband analog signals and recover the transmitted data from the baseband signals; the receiver circuit including a baseband processor to convert the baseband analog signals into digital output vector streams, wherein the baseband processor comprises a single ADC (Analog to Digital Converter) circuit arranged to alternately sample the baseband analog signals to form the digital output vector streams; and an alignment circuit to align a phase relation of the digital output vector streams so as to compensate for phase difference introduced by said single ADC circuit, wherein the ADC circuit alternately samples the baseband analog signals during first and second time intervals that are each equal to a predetermined ADC sample period corresponding to a sample clock cycle; and said compensating for the phase difference includes delaying one of the digital output vector streams for ½
clock cycle.
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17. A baseband processor, comprising:
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means for receiving a first analog signal encoding a first data stream; means for receiving a second input to receive a second analog signal encoding a second data stream, the fast and second analog signals having a predetermined phase relationship; means for selecting one at a time of the first and second analog signals; means for converting the selected analog signal so as to generate digital data; means for steering the digital data generated by said converting means to a selected one of a first means for providing a digital output and a second means for providing a digital output, responsive to a demultiplexer control signal; and means for aligning a phase relation of the digital data provided by said steering means at the first and second digital outputs responsive to the said predetermined phase relationship of the first and second analog signals so as to compensate for phase difference introduced by said means for converting, wherein the means for converting samples the selected analog signal during one of first and second time intervals that are each equal to a predetermined ADC (Analog to Digital Converter) sample period corresponding to a sample clock cycle; and said compensating for the phase difference includes delaying the digital data for ½
clock cycle. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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25. A wireless transceiver, comprising:
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means for encoding and transmitting data modulated onto at least one selected RF (radio frequency) band; and means for receiving signals on the selected RF band, demodulating the received signals to form a pair of baseband analog signals and recovering the transmitted data from the baseband signals; the receiving, demodulating and recovering means including means for converting the baseband analog signals into digital output vector streams, wherein the converting means comprises a single ADC (Analog to Digital Converter) means for alternately sampling the baseband analog signals to form the digital output vector streams, and alignment means for aligning a phase relation of the digital output vector streams so as to compensate for phase difference introduced by said single ADC means, wherein the single ADC means alternately samples the baseband analog signals during first and second time intervals that are each equal to a predetermined ADC sample period corresponding to a sample clock cycle; and said compensating for the phase difference includes delaying one of the digital output vector streams for ½
clock cycle. - View Dependent Claims (26, 27)
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28. A network interface apparatus, comprising:
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means for interfacing a network; and a wireless transceiver responsive to said interfacing means, said wireless transceiver comprising; means for encoding and transmitting data modulated onto at least one selected RF (radio frequency) band; and means for receiving signals on the selected RF band, demodulating the received signals to form a pair of baseband analog signals and recovering the transmitted data from the baseband signals; the receiving, demodulating and recovering means including means for converting the baseband analog signals into digital output vector streams, wherein the converting means comprises a single ADC (Analog to Digital Converter) means for alternately sampling the baseband analog signals to form the digital output vector streams and alignment means for aligning a phase relation of the digital output vector streams so as to compensate for phase difference introduced by said single ADC means, wherein the single ADC means alternately samples the baseband analog signals during first and second time intervals that are each equal to a predetermined ADC sample period corresponding to a sample clock cycle; and said compensating for the phase difference includes delaying one of the digital output vector streams for ½
clock cycle.
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29. An information processing apparatus, comprising:
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means for processing information; and a network interface apparatus responsive to said means for processing information, the network interface apparatus comprising; means for interfacing a network; and a wireless transceiver responsive to said interfacing means, said wireless transceiver comprising; means for encoding and transmitting data modulated onto at least one selected RF (radio frequency) band; and means for receiving signals on the selected RF band, demodulating the received signals to form a pair of baseband analog signals and recovering the transmitted data from the baseband signals; the receiving, demodulating and recovering means including means for converting the baseband analog signals into digital output vector streams, wherein the converting means comprises a single ADC (Analog to Digital Converter) means for alternately sampling the baseband analog signals to form the digital output vector streams and alignment means for aligning a phase relation of the digital output vector streams so as to compensate for phase difference introduced by said single ADC means, wherein the single ADC means alternately samples the baseband analog signals during first and second time intervals that are each equal to a predetermined ADC sample period corresponding to a sample clock cycle; and said compensating for the phase difference includes delaying one of the digital output vector streams for ½
clock cycle.
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Specification