ADC architecture for wireless applications

• US 7,388,931 B1
• Filed: 06/12/2002
• Issued: 06/17/2008
• Est. Priority Date: 06/12/2002
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Hsu, Yungping, Yu, Mao
• Primary Examiner(s): Ghayour; Mohammed
• Assistant Examiner(s): Vlahos; Sophia
• Application Number:
  US10/170,306
• Time in Patent Office: 2,197 Days
• Field of Search: 341/144, 341/143, 341/61, 341/77, 341/50, 341/54, 341/120, 341/123, 341/138, 327/105, 375/354, 375/377, 375/355, 375/222, 375/242, 375/326, 375/316, 375/235, 375/347, 375/285, 375/296, 375/220, 375/340, 375/350, 708/213, 708/300, 455/295, 455/296, 455/141, 348/607, 348/726, 348/638, 348/608, 348609-612
• US Class Current: 375/316
• CPC Class Codes: H03M 1/1225 using time-division multiplexing
• CPC Class Codes: H04L 27/38 Demodulator circuits; Receiver circuits

Abstract

A simplified architecture is disclosed for ADC conversion of received in-phase I and quadrature Q signals. Circuit area is substantially reduced by sharing a single ADC to convert both signals, switching the ADC input alternately between the i and q signals. In an embodiment, the ADC is clocked at an increased sample rate, and the digital output signals are aligned to compensate for the phase difference resulting from the implementation of a single ADC. Aligning includes delaying one of the digital signals, and interpolating the other one of the digital signals in a low pass filter so as to compensate for the phase difference introduced by the sampling during the first and second time intervals. The first and second time intervals are equal to a predetermined ADC sample period corresponding to a sample clock cycle. Delaying the first digital signal includes a delay of 1/2 clock cycle.

Claims

1. A method of concurrently converting a substantially orthogonal pair of analog signals having a predetermined nominal phase relationship into corresponding digital signals in a baseband processor, using only a single ADC (Analog to Digital Converter) circuit, the method comprising:

providing a single ADC circuit;

during a first time interval, sampling a first one of the analog signals in the ADC circuit to provide a first digital signal;

during a second time interval non-overlapping the first time interval, sampling the other one of the pair of analog signals in the ADC circuit to provide a second digital signal; and

aligning the first and second digital signals so as to compensate for phase difference introduced by said sampling during the first and second time intervals, wherein said aligning comprises;

delaying a first one of the digital signals; and

interpolating the other one of the digital signals in a LPF (Low Pass Filter), so as to compensate for the phase difference introduced by said sampling during the first and second time intervals,

wherein each of the first and second time intervals is equal to a predetermined ADC sample period corresponding to a sample clock cycle; and

said delaying the first digital signal comprises a delay of ½

clock cycle.

2. The method of claim 1, wherein delaying the second digital signal comprises a delay of (2k+1)/2 clock cycles, where k is an integer.

3. The method of claim 1, further comprising buffering the first and second analog signals in a common buffer prior to said sampling during the first and second time intervals.

4. The method of claim 1, further comprising buffering the first and second analog signals in first and second buffers, respectively, prior to said sampling during the first and second time intervals.

5. A baseband processor, comprising:

a first input to receive a first analog signal encoding a first data stream;

a second input to receive a second analog signal encoding a second data stream, the first and second analog signals having a predetermined phase relationship;

a multiplexer responsive to the first and second inputs and arranged to select one at a time of the first and second analog signals;

an ADC (Analog to Digital Converter) circuit to convert the selected analog signal so as to generate digital data;

a demultiplexer circuit to steer the digital data generated by the ADC to a selected one of a first digital output and a second digital output, responsive to a demultiplexer control signal; and

an alignment circuit to align a phase relation of the digital data provided by the demultiplexer at the first and second digital outputs such that the phase relation is substantially the same as said predetermined phase relationship of the first and second analog signals so as to compensate for phase difference introduced by said ADC circuit,

wherein the ADC circuit converts the selected analog signal during one of first and second time intervals that are each equal to a predetermined ADC sample period corresponding to a sample clock cycle; and

said compensating for the phase difference includes delaying the digital data for ½

clock cycle.

6. The baseband processor of claim 5, wherein:

said multiplexer selects one at a time of the first and second analog signals responsive to a multiplexer control signal;

wherein said demultiplexer steers the digital data generated by said ADC responsive to a demultiplexer control signal; and

wherein both the multiplexer control signal and the demultiplexer control signal are synchronized to operation of said ADC, such that the digital data generated by the ADC responsive the first analog signal is steered to said first digital output and the digital data generated by said ADC responsive to the second analog signal is steered to said second digital output.

7. The baseband processor of claim 6, further comprising:

a first buffer interposing the first input and the multiplexer to buffer the first analog signal; and

a second buffer interposing the second input and the multiplexer to buffer the analog signal.

8. The baseband processor of claim 6, further comprising a buffer interposing said multiplexer and said ADC and arranged to buffer the selected analog signal.

9. The baseband processor of claim 6, wherein the alignment circuit includes a delay circuit in series with a first one of the digital outputs.

10. The baseband processor of claim 6, wherein the alignment circuit includes a delay circuit in series with a first one of the digital outputs and an interpolator LPF circuit in series with the other one of the digital outputs.

11. The baseband processor of claim 6, wherein the ADC circuit comprises a pipelined ADC.

12. The baseband processor of claim 6, further comprising a sampling clock circuit for driving the ADC at a sample rate on the order of 88 MHz.

13. A wireless transceiver, comprising:

a transmitter circuit to encode and transmit data modulated onto at least one selected RF (radio frequency) band; and

a receiver circuit to receive signals on the selected RF band, demodulate the received signals to form a pair of baseband analog signals and recover the transmitted data from the baseband signals;

the receiver circuit including a baseband processor to convert the baseband analog signals into digital output vector streams, wherein the baseband processor comprises a single ADC (Analog to Digital Converter) circuit arranged to alternately sample the baseband analog signals to form the digital output vector streams and a phase adjustment circuit to align the first and second digital output vector streams so as to compensate for a phase difference introduced by said alternately sampling the baseband analog signals to form the digital output vector streams,

wherein the ADC circuit alternately samples the baseband analog signals during first and second time intervals that are each equal to a predetermined ADC sample period corresponding to a sample clock cycle; and

said compensating for the phase difference includes delaying one of the first and second digital output vector streams for ½

clock cycle.

14. The wireless transceiver of claim 13, wherein the transmitter circuit transmits the data in the form of at least one of Barker, CCK (Complementary Code Keying), and OFDM (Orthogonal Frequency Division Multiplexing) symbols.

15. A network interface apparatus, comprising:

a network interface; and

a wireless transceiver responsive to said network interface, said wireless transceiver comprising;

a transmitter circuit to encode and transmit data modulated onto at least one selected RF (radio frequency) band; and

a receiver circuit to receive signals on the selected RF band, demodulate the received signals to form a pair of baseband analog signals and recover the transmitted data from the baseband signals;

the receiver circuit including a baseband processor to convert the baseband analog signals into digital output vector streams, wherein the baseband processor comprises a single ADC (Analog to Digital Converter) circuit arranged to alternately sample the baseband analog signals to form the digital output vector streams; and

an alignment circuit to align a phase relation of the digital output vector streams so as to compensate for phase difference introduced by said single ADC circuit,

wherein the ADC circuit alternately samples the baseband analog signals during first and second time intervals that are each equal to a predetermined ADC sample period corresponding to a sample clock cycle; and

said compensating for the phase difference includes delaying one of the digital output vector streams for ½

clock cycle.

16. An information processing apparatus, comprising:

an information processor; and

a network interface apparatus responsive to said processor, the network interface apparatus comprising;

a network interface; and

a wireless transceiver responsive to said network interface, said wireless transceiver comprising;

a transmitter circuit to encode and transmit data modulated onto at least one selected RF (radio frequency) band; and

a receiver circuit to receive signals on the selected RF band, demodulate the received signals to form a pair of baseband analog signals and recover the transmitted data from the baseband signals;

the receiver circuit including a baseband processor to convert the baseband analog signals into digital output vector streams, wherein the baseband processor comprises a single ADC (Analog to Digital Converter) circuit arranged to alternately sample the baseband analog signals to form the digital output vector streams; and

an alignment circuit to align a phase relation of the digital output vector streams so as to compensate for phase difference introduced by said single ADC circuit,

wherein the ADC circuit alternately samples the baseband analog signals during first and second time intervals that are each equal to a predetermined ADC sample period corresponding to a sample clock cycle; and

said compensating for the phase difference includes delaying one of the digital output vector streams for ½

clock cycle.

17. A baseband processor, comprising:

means for receiving a first analog signal encoding a first data stream;

means for receiving a second input to receive a second analog signal encoding a second data stream, the fast and second analog signals having a predetermined phase relationship;

means for selecting one at a time of the first and second analog signals;

means for converting the selected analog signal so as to generate digital data;

means for steering the digital data generated by said converting means to a selected one of a first means for providing a digital output and a second means for providing a digital output, responsive to a demultiplexer control signal; and

means for aligning a phase relation of the digital data provided by said steering means at the first and second digital outputs responsive to the said predetermined phase relationship of the first and second analog signals so as to compensate for phase difference introduced by said means for converting,

wherein the means for converting samples the selected analog signal during one of first and second time intervals that are each equal to a predetermined ADC (Analog to Digital Converter) sample period corresponding to a sample clock cycle; and

said compensating for the phase difference includes delaying the digital data for ½

clock cycle.

18. The baseband processor of claim 17, wherein:

said selecting means selects one at a time of the first and second analog signals responsive to a multiplexer control signal;

wherein said steering means steers the digital data generated by said converting means responsive to a demultiplexer control signal; and

wherein both the multiplexer control signal and the demultiplexer control signal are synchronized to operation of said converting means, such that the digital data generated by the converting means responsive the first analog signal is steered to said first digital output and the digital data generated by said converting means responsive to the second analog signal is steered to said second digital output.

19. The baseband processor of claim 18, further comprising:

means for buffering the first analog signal; and

means for buffering the second analog signal.

20. The baseband processor of claim 18, further comprising means for buffering the selected analog signal.

21. The baseband processor of claim 18, wherein the alignment circuit includes a delay circuit in series with a first one of the digital outputs.

22. The baseband processor of claim 18, wherein said aligning means includes means for delaying in series with a first one of the means for providing the digital outputs and an interpolator LPF (Low Pass Filter) means in series with the other one of means for providing the digital outputs.

23. The baseband processor of claim 18, wherein the converting means comprises a pipelined converting means.

24. The baseband processor of claim 18, further comprising means for sampling a clock circuit for driving the converting means at a sample rate on the order of 88 MHz.

25. A wireless transceiver, comprising:

means for encoding and transmitting data modulated onto at least one selected RF (radio frequency) band; and

means for receiving signals on the selected RF band, demodulating the received signals to form a pair of baseband analog signals and recovering the transmitted data from the baseband signals;

the receiving, demodulating and recovering means including means for converting the baseband analog signals into digital output vector streams, wherein the converting means comprises a single ADC (Analog to Digital Converter) means for alternately sampling the baseband analog signals to form the digital output vector streams, and alignment means for aligning a phase relation of the digital output vector streams so as to compensate for phase difference introduced by said single ADC means,

wherein the single ADC means alternately samples the baseband analog signals during first and second time intervals that are each equal to a predetermined ADC sample period corresponding to a sample clock cycle; and

said compensating for the phase difference includes delaying one of the digital output vector streams for ½

clock cycle.

26. The wireless transceiver of claim 25, wherein the encoding and transmitting means transmits the data in the form of at least one of Barker, CCK (Complementary Code Keying), and OFDM (Orthogonal Frequency Division Multiplexing) symbols.

27. The wireless transceiver of claim 25, wherein the converting means includes means for aligning the first and second digital output vector streams so as to compensate for a phase difference introduced by said alternately sampling the baseband analog signals in forming the digital output vector streams.

28. A network interface apparatus, comprising:

means for interfacing a network; and

a wireless transceiver responsive to said interfacing means, said wireless transceiver comprising;

means for encoding and transmitting data modulated onto at least one selected RF (radio frequency) band; and

means for receiving signals on the selected RF band, demodulating the received signals to form a pair of baseband analog signals and recovering the transmitted data from the baseband signals;

the receiving, demodulating and recovering means including means for converting the baseband analog signals into digital output vector streams, wherein the converting means comprises a single ADC (Analog to Digital Converter) means for alternately sampling the baseband analog signals to form the digital output vector streams and alignment means for aligning a phase relation of the digital output vector streams so as to compensate for phase difference introduced by said single ADC means,

wherein the single ADC means alternately samples the baseband analog signals during first and second time intervals that are each equal to a predetermined ADC sample period corresponding to a sample clock cycle; and

said compensating for the phase difference includes delaying one of the digital output vector streams for ½

clock cycle.

29. An information processing apparatus, comprising:

means for processing information; and

a network interface apparatus responsive to said means for processing information, the network interface apparatus comprising;

means for interfacing a network; and

a wireless transceiver responsive to said interfacing means, said wireless transceiver comprising;

means for encoding and transmitting data modulated onto at least one selected RF (radio frequency) band; and

means for receiving signals on the selected RF band, demodulating the received signals to form a pair of baseband analog signals and recovering the transmitted data from the baseband signals;

the receiving, demodulating and recovering means including means for converting the baseband analog signals into digital output vector streams, wherein the converting means comprises a single ADC (Analog to Digital Converter) means for alternately sampling the baseband analog signals to form the digital output vector streams and alignment means for aligning a phase relation of the digital output vector streams so as to compensate for phase difference introduced by said single ADC means,

wherein the single ADC means alternately samples the baseband analog signals during first and second time intervals that are each equal to a predetermined ADC sample period corresponding to a sample clock cycle; and

said compensating for the phase difference includes delaying one of the digital output vector streams for ½

clock cycle.