Dedicated interface architecture for a hybrid integrated circuit

• US 7,389,487 B1
• Filed: 04/28/1998
• Issued: 06/17/2008
• Est. Priority Date: 04/28/1998
• Status: Expired due to Fees

• Current Assignee: Microsemi SoC Corp.
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Chan, King W., Cheng, Chi Fung, Kaptanoglu, Sinan, Shu, William C. T.
• Primary Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US09/069,054
• Time in Patent Office: 3,703 Days
• Field of Search: 395/500.17, 716/16, 716/12, 326/39
• US Class Current: 716/50
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: H03K 19/177 arranged in matrix form

Abstract

An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.

Claims

1. An interface architecture in an integrated circuit comprising:

an FPGA portion of said integrated circuit having logic blocks for implementing logic functions and interconnect conductors for programmably connecting said logic blocks

an ASIC portion of said integrated circuit having mask programmed logic circuits and mask programmed interconnect conductors between said logic circuits;

mask programmed dedicated interface tracks connected between said logic blocks in said FPGA portion and said mask programmed interconnect conductors in said ASIC portion; and

interface buffers disposed in series with said dedicated interface tracks between said FPGA portion and said ASIC portion, each interface buffer including an input buffer, an output buffer connected to said input buffer, three multiplexers, two of said multiplexers connected to said output buffer and one of said multiplexers connected to said input buffer.

2. The interface architecture of claim 1, wherein interconnect conductors in said FPGA portion include local routing resources.

3. The interface architecture of claim 1 wherein each of said interface buffers further includes a configurable register, said configurable register connected to the select inputs of each of said multiplexers.

4. The interface architecture of claim 1 wherein each of said interface buffers further includes a memory store, said memory store connected to the select inputs of each of said multiplexers.

5. The interface architecture of claim 1 wherein each of said interface buffers further includes programmable elements, said programmable elements connected to the select inputs of each of said multiplexers.

6. The interface architecture of claim 1, further including an FPGA-ASIC routing channel arranged between said dedicated interface tracks and said ASIC portion.

7. The interface architecture of claim 6, wherein said FPGA-ASIC routing channel is mask-programmable.

8. The interface architecture of claim 6, wherein said FPGA-ASIC routing channel is field-programmable.

9. The interface architecture of claim 8, further including a plurality of I/O modules arranged on the perimeter of the IC.

10. The interface architecture of claim 9, wherein one or more of said I/O modules are connected to said FPGA-ASIC routing channel.

11. The interface architecture IC of claim 1, further including JTAG buffers arranged between said dedicated interface tracks and said ASIC portion.

12. The interface architecture of claim 1, further including a plurality of I/O modules arranged on the perimeter of the IC.

13. The interface architecture of claim 12, wherein one or more of said I/O modules are connected to said FPGA portion through a routing channel.

14. The interface architecture of claim 12, wherein one or more of said I/O modules are connected to said ASIC portion.

15. The interface architecture of claim 1, wherein said ASIC portion is adjacent to one side of said FPGA portion.

16. The interface architecture of claim 1, wherein said ASIC portion is adjacent to two sides of said FPGA portion.

17. The interface architecture of claim 1, wherein said ASIC portion is adjacent to three sides of said FPGA portion.

18. The interface architecture of claim 1, wherein said ASIC portion is adjacent to four sides of said FPGA portion.

19. The interface architecture of claim 1, wherein said FPGA portion has a hierarchial design including a plurality of levels, each of said levels containing local routing resources and a plurality of blocks, each of said blocks including either a module or another of said levels.

20. An interface architecture in an integrated circuit comprising:

an FPGA portion of said integrated circuit having a plurality of levels, each of said levels containing local routing resources and a plurality of blocks, each of said blocks including either a module or another of said levels;

an ASIC portion of said integrated circuit having mask programmed interconnect conductors between logic portions of said ASIC portion;

mask programmed dedicated interface tracks connected between said modules or blocks in said FPGA portion and said mask programmed interconnect conductors in said ASIC portion and

interface buffers arranged between said dedicated interface tracks and said ASIC portion, each interface buffer including an input buffer, an output buffer connected to said input buffer, three multiplexers, two of said multiplexers connected to said output buffer and one of said multiplexers connected to said input buffer.

21. The interface architecture of claim 20, wherein each of said blocks in said FPGA portion contains local routing resources.

22. The interface architecture of claim 20 wherein each of said interface buffers further includes a configurable register, said configurable register connected to the select inputs of each of said multiplexers.

23. The interface architecture of claim 20 wherein each of said interface buffers further includes a memory store, said memory store connected to the select inputs of each of said multiplexers.

24. The interface architecture of claim 20 wherein each of said interface buffers further includes programmable elements, said programmable elements connected to the select inputs of each of said multiplexers.

25. The interface architecture of claim 20, further including an FPGA-ASIC routing channel arranged between said dedicated interface tracks and said ASIC portion.

26. The interface architecture of claim 25, wherein said FPGA-ASIC routing channel is mask-programmable.

27. The interface architecture of claim 25, wherein said FPGA-ASIC routing channel is field-programmable.

28. The interface architecture of claim 27, further including a plurality of I/O modules arranged on the perimeter of the integrated circuit.

29. The interface architecture of claim 28, wherein one or more of said I/O modules are connected to said FPGA-ASIC routing channel.

30. The interface architecture of claim 20, further including JTAG buffers arranged between said dedicated interface tracks and said ASIC portion.

31. The interface architecture of claim 20, further including a plurality of I/O modules arranged on the perimeter of the IC.

32. The interface architecture of claim 31, wherein one or more of said I/O modules are connected to said FPGA portion through a routing channel.

33. The interface architecture of claim 31, wherein one or more of said I/O modules are connected to said ASIC portion.

34. The interface architecture of claim 20, wherein said ASIC portion is adjacent to one side of said FPGA portion.

35. The interface architecture of claim 20, wherein said ASIC portion is adjacent to two sides of said FPGA portion.

36. The interface architecture of claim 20, wherein said ASIC portion is adjacent to three sides of said FPGA portion.

37. The interface architecture of claim 20, wherein said ASIC portion is adjacent to four sides of said FPGA portion.