Semiconductor device and manufacturing method thereof

• US 7,390,688 B2
• Filed: 02/08/2006
• Issued: 06/24/2008
• Est. Priority Date: 02/21/2005
• Status: Expired due to Fees

• Current Assignee: Casio Computer Company Limited
• Original Assignee: Casio Computer Company Limited
• Inventors: Mihara, Ichiro, Wakabayashi, Takeshi
• Primary Examiner(s): Cao; Phat X
• Application Number:
  US11/349,779
• Publication Number:
  US 20060186542A1
• Time in Patent Office: 867 Days
• Field of Search: 438/68, 438/113, 438/110, 257/E21.503
• US Class Current: 438/68
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device includes a semiconductor substrate which has an integrated circuit formed on a front surface thereof, and a rough surface with a height difference of 1 to 5 μm on a rear surface thereof. A protective film is provided on the rear surface of the semiconductor substrate.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming columnar electrodes on a semiconductor wafer;

forming a sealing film on the semiconductor wafer between peripheries of the columnar electrodes;

grinding a rear surface of the semiconductor wafer;

cutting from a rear surface side of the semiconductor wafer to at least a halfway point of the sealing film to form grooves for separating the semiconductor wafer into individual semiconductor substrates;

roughening the rear surface and side surface of the semiconductor wafer by wet etching;

forming a protective film on the rear surface of the semiconductor wafer and inside of the grooves; and

cutting the protective film formed in the grooves to obtain a plurality of semiconductor devices.

2. The method according to claim 1, wherein the protective film is formed of a resin.

3. The method according to claim 1, wherein the protective film is formed of a metal.

4. The method according to claim 1, wherein the semiconductor wafer has an integrated surface formed on a front surface thereof, which is opposite to the rear surface.

5. The method according to claim 4, wherein the columnar electrodes are formed on the front surface of the semiconductor wafer.

6. The method according to claim 1, wherein the rear surface of the semiconductor wafer is roughened to be a rough surface with a height difference of 1 to 5 μ

m.

7. The method according to claim 1, wherein the rear surface and the side surface of the semiconductor wafer are roughened to be rough surfaces with a height difference of 1 to 5 μ

m.

8. The method according to claim 1, wherein the rear surface and the side surface of the semiconductor wafer are roughened to be rough surfaces having a plurality of concave and convex portions, and wherein a height difference between a base of each of the concave portions to a top of an adjacent one of the convex portions is 1 to 5 μ

m.

9. The method according to claim 8, wherein the convex portions are substantially arc-shaped.

10. The method according to claim 1, further comprising forming a solder ball on each of the columnar electrodes.

11. The method according to claim 10, wherein the solder balls are formed on the columnar electrodes before the cutting to obtain the semiconductor devices is performed.

12. The method according to claim 1, wherein said cutting to obtain the semiconductor devices comprises cutting through the sealing film above the grooves.

13. The method according to claim 12, wherein in each of the semiconductor devices obtained by said cutting, a side surface of the sealing film obtained by said cutting forms one surface together with a side surface of the protective film obtained by said cutting.

14. The method according to claim 1, wherein the semiconductor wafer includes a plurality of connection pads, wherein the method further comprises forming wiring connected to the connection pads, and wherein the columnar electrodes are formed on the wiring.

15. The method according to claim 14, further comprising forming an insulating film on a front surface, opposite to the rear surface, of the semiconductor wafer, and forming a protective film on the insulating film;

wherein the wiring is formed on the protective film and is connected to the connection pads through holes in the protective film and the insulating film.

16. The method according to claim 15, wherein an integrated circuit is formed on the front surface of the semiconductor wafer, and the connection pads are connected to the integrated circuit.

17. A method of manufacturing a semiconductor device, comprising:

forming columnar electrodes to be connected to connection pads on a front surface of a semiconductor wafer;

forming a sealing film between peripheries of the columnar electrodes;

grinding a rear surface of the semiconductor wafer to reduce a thickness of the semiconductor wafer;

cutting from a rear surface side of the semiconductor wafer to at least a halfway point of the sealing film to form grooves;

roughening the rear surface and side surface of the semiconductor wafer by wet etching;

forming a protective film on the rear surface of the semiconductor wafer and inside of the grooves; and

cutting the protective film formed in the grooves and the sealing film provided above the grooves to obtain a plurality of semiconductor devices.