High voltage silicon carbide devices having bi-directional blocking capabilities

• US 7,391,057 B2
• Filed: 05/18/2005
• Issued: 06/24/2008
• Est. Priority Date: 05/18/2005
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Agarwal, Anant K., Hobgood, Hudson McDonald, Ryu, Sei-Hyung, Das, Mrinal K., Palmour, John W., Jenny, Jason R.
• Primary Examiner(s): Pham; Hoai V
• Application Number:
  US11/131,509
• Publication Number:
  US 20060261345A1
• Time in Patent Office: 1,133 Days
• Field of Search: 257/77, 257/107, 257147-148, 257150-153, 257/155
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/74 Thyristor-type devices, e.g. having four-zone regenerative action two-terminal thyristors H01L29/87

Abstract

High voltage silicon carbide (SiC) devices, for example, thyristors, are provided. A first SiC layer having a first conductivity type is provided on a first surface of a voltage blocking SiC substrate having a second conductivity type. A first region of SiC is provided on the first SiC layer and has the second conductivity type. A second region of SiC is provided in the first SiC layer. The second region of SiC has the first conductivity type and is adjacent to the first region of SiC. A second SiC layer having the first conductivity type is provided on a second surface, opposite the first surface, of the voltage blocking SiC substrate. First, second and third contacts are provided on the first region of SiC, the second region of SiC and the second SiC layer, respectively. Related methods of fabricating high voltage SiC devices are also provided.

Claims

1. A high voltage silicon carbide (SiC) device, comprising:

a first SiC layer having a first conductivity type on a first surface of a voltage blocking SiC substrate having a second conductivity type;

a first region of SiC on the first SiC layer and having the second conductivity type;

a second region of SiC in the first SiC layer, having the first conductivity type and being adjacent to the first region of SiC;

a second SiC layer having the first conductivity type on a second surface, opposite the first surface, of the voltage blocking SiC substrate; and

first and second contacts on the first region of SiC and the second SiC layer, respectively.

2. The device of claim 1, wherein the voltage blocking substrate comprises a 4H—

SiC high purity substrate having a carrier concentration no greater than about 1.0×

10¹⁵ cm<sup>−

3</sup>.

3. The device of claim 2, wherein the voltage blocking substrate has a thickness of greater than about 100 μ

m.

4. The device of claim 1, wherein the first conductivity type comprises p-type SiC and the second conductivity type comprises n-type SiC.

5. The device of claim 1, wherein the first conductivity type comprises n-type SiC and the second conductivity type comprises p-type SiC.

6. The device of claim 1:

wherein the first SiC layer has a carrier concentration of from about 1.0×

10¹⁵ cm<sup>−

3</sup> to about 1.0×

10¹⁹ cm<sup>−

3</sup>; and

wherein the second SiC layer has a carrier concentration of from about 1.0×

10¹⁷ cm<sup>−

3</sup> to about 1.0×

10²¹ cm<sup>−

3</sup>; and

wherein the first region of SiC has a carrier concentration of from about 1.0×

10¹⁶ cm<sup>−

3</sup> to about 1.0×

10²¹ cm⁻

.

7. The device of claim 1:

wherein the first SiC layer has a thickness of from about 0.1 μ

m to about 20.0 μ

m;

wherein the second SiC layer has thickness of from about 0.5 μ

m to about 50.0 μ

m; and

wherein the first region of SiC has a thickness of from about 0.1 μ

m to about 10.0 μ

m.

8. The device of claim 1, wherein the SiC device comprises a thyristor, wherein the first region of SiC comprises an anode region of the thyristor, wherein the second region of SiC comprises a gate region of the thyristor and wherein the second SiC layer comprises a cathode region of the thyristor.

9. The device of claim 8, further comprising a third contact on the second region of SiC, wherein the first, second and third contacts comprise an anode contact, a cathode contact and a gate contact, respectively, the device further comprising first, second and third overlayers on the first, second and third contacts, respectively.

10. The device of claim 1, wherein the second region of SiC has a carrier concentration of from about 1.0×

10¹⁷ cm<sup>−

3</sup> to about 1.0×

10²¹ cm<sup>−

3</sup> and extends into the first SiC layer from about 0.1 μ

m to about 2.0 μ

m.

11. The device of claim 1, wherein the voltage blocking substrate is a bi-directional voltage blocking layer and has an edge termination structure.

12. The device of claim 11, wherein the voltage blocking substrate is a boule grown substrate.

13. The device of claim 1, wherein the edge termination provides:

a first blocking junction between the first surface of the voltage blocking substrate and the first SiC layer; and

a second blocking junction between the second surface of the voltage blocking substrate and the second SiC layer.

14. A silicon carbide (SiC) thyristor, comprising:

a first SiC layer having a first conductivity type on a first surface of a voltage blocking SIC substrate having a second conductivity type;

a SiC anode region on the first SiC layer and having the second conductivity type;

a SiC gate region in the first SiC layer, having the first conductivity type and being adjacent to the SiC anode region;

a SiC cathode layer having the first conductivity type on a second surface, opposite the first surface, of the voltage blocking SiC substrate; and

an anode contact, a gate contact and a cathode contact on the SiC anode region, the SiC gate region and the SiC cathode layer, respectively.

15. The thyristor of claim 14, wherein the voltage blocking substrate is a bi-directional voltage blocking layer and has a edge termination structure.

16. The thyristor of claim 15, wherein the edge termination structure provides:

a first blocking junction between the first surface of the voltage blocking substrate and the first SiC layer; and

a second blocking junction between the second surface of the voltage blocking substrate and the SiC cathode layer.

17. A high voltage silicon carbide (SiC) device, comprising:

a first SiC layer having a first conductivity type on a first surface of a voltage blocking SiC epilayer having a second conductivity type;

a first region of SiC on the first SiC layer and having the second conductivity type;

a second region of SIC in the first SiC layer, having the first conductivity type and being adjacent to the first region of SiC;

a second SiC layer having the first conductivity type on a second surface, opposite the first surface, of the voltage blocking SiC epilayer; and

first and second contacts on the first region of SiC and the second SiC layer, respectively.

18. A silicon carbide (SiC) thyristor, comprising:

a first SiC layer having a first conductivity type on a first surface of a voltage blocking SiC epilayer having a second conductivity type;

a SiC anode region on the first SiC layer and having the second conductivity type;

a SiC gate region in the first SiC layer, having the first conductivity type and being adjacent to the SiC anode region;

a SiC cathode layer having the first conductivity type on a second surface, opposite the first surface, of the voltage blocking SiC epilayer; and

an anode contact, a gate contact and a cathode contact on the SiC anode region, the SiC gate region and the SiC cathode layer, respectively.