Non-volatile memory cells

• US 7,391,076 B2
• Filed: 02/22/2007
• Issued: 06/24/2008
• Est. Priority Date: 05/26/2003
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ozawa, Yoshio
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US11/709,160
• Publication Number:
  US 20070145471A1
• Time in Patent Office: 488 Days
• Field of Search: 257/315, 257/316, 257/317, 257/E29.129
• US Class Current: 257/317
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film provided on the semiconductor substrate, a floating gate electrode provided on the tunnel insulating film, the width of the floating gate electrode changing in the height direction of the non-volatile memory cell in channel width or length direction there, and being thinnest between a region above the bottom surface of the floating gate electrode and a region below the upper surface thereof, a control gate electrode above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

Claims

1. A semiconductor device comprising:

a semiconductor substrate provided with an isolation trench filled with an isolation film; and

a plurality of non-volatile memory cells provided on the semiconductor substrate,

each of the plurality of non-volatile memory cells comprising;

a tunnel insulating film provided on the semiconductor substrate;

a floating gate electrode provided on the tunnel insulating film, a width of the floating gate electrode changing in a height direction of the non-volatile memory cells in a channel width direction, and being thinnest between a region above a bottom surface of the floating gate electrode and a region below an upper surface thereof,

a control gate electrode above the floating gate electrode; and

an interelectrode insulating film provided between the control gate electrode and the floating gate electrode,

wherein the plurality of non-volatile memory cells includes a first non-volatile memory cell including a first floating gate electrode and a second non-volatile memory cell, adjacent to the first non-volatile memory cell, including a second floating gate electrode,

the isolation film covers lower side portions of the first and second floating gate electrodes in the channel width direction and the isolation film includes a top surface which is higher than a surface of the semiconductor substrate, and

the first and second floating gate electrodes include portions whose widths in the channel width direction increase toward downward from a first position where the top surface of the isolation film contacts the first floating gate electrode and a second position where the top surface of the isolation film contacts the second floating gate electrode.