Apparatus and method for minimizing power loss associated with dead time

• US 7,391,194 B2
• Filed: 02/16/2005
• Issued: 06/24/2008
• Est. Priority Date: 02/20/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Brown, James S
• Primary Examiner(s): Han; Jessica
• Application Number:
  US11/058,969
• Publication Number:
  US 20050184716A1
• Time in Patent Office: 1,224 Days
• Field of Search: 323/222, 323/282, 323/283, 323/271, 323/351, 327/175, 363/53, 363/89, 363/127
• US Class Current: 323/283
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Apparatus for minimizing power losses associated with dead time between ON times of two series connected switches of a power converter connected across a supply potential, the apparatus comprising a control arrangement for monitoring a selected parameter associated with power loss during the dead time of the converter; the control arrangement changing the dead time from a first dead time to a second dead time and comparing power loss associated with the selected parameter for the first and second dead times and determining which of the power losses associated with the two dead times is smaller; a dead time implementing stage for implementing the two dead times; and the control arrangement selecting the dead time associated with the smaller power loss and providing a signal to the dead time implementing stage to set the selected dead time.

Claims

1. Apparatus for minimizing power losses associated with dead time between ON times of two series connected switches of a power converter connected across a supply potential, the apparatus comprising:

a control arrangement for monitoring a selected parameter associated with power loss during the dead time of the converter;

the control arrangement changing the dead time from a first dead time to a second dead time and comparing power loss associated with the selected parameter for the first and second dead times and determining which of the power losses associated with the two dead times is smaller;

a dead time implementing stage for implementing the two dead times; and

the control arrangement selecting the dead time associated with the smaller power loss and providing a signal to the dead time implementing stage to set the selected dead time.

2. The apparatus of claim 1, wherein the dead time implementing stage implements a variable turn-off of a control signal to one of the switches and a variable turn-on of the control signal to said one of the switches.

3. The apparatus of claim 2, wherein the one of the switches performs a synchronous rectification function and the other switch is a control switch.

4. The apparatus of claim 2, wherein the control arrangement comprises a module sampling the pulse width modulated signal at selected instants in time corresponding to the first and second dead times;

and a processor for controlling timing of the sampling.

5. The apparatus of claim 4, wherein the sampling module comprises a sample and hold module.

6. The apparatus of claim 4, wherein the sampling module comprises a digital memory.

7. The apparatus of claim 4, wherein the control arrangement further comprises a comparator having one input coupled to an output of the sample and hold module and a second input coupled to an input to the sample and hold module whereby the comparator compares first and second time delayed samples of said pulse width modulated signal and determines which of the samples is associated with a smaller power loss.

8. The apparatus of claim 7, wherein a reduced duty cycle is associated with a smaller power loss.

9. The apparatus of claim 7, wherein said control arrangement further comprises a modulator stage for modulating the supply potential with said pulse width modulated signal to produce a signal proportional to the duty cycle of the pulse width modulated signal.

10. The apparatus of claim 9, wherein the modulator stage comprises a multiplier.

11. The apparatus of claim 9, wherein said control arrangement further comprises a low pass filter converting said signal proportional to the duty cycle to a filtered signal corresponding to the output voltage of the converter if there were no converter losses.

12. The apparatus of claim 4, wherein the dead time implementing stage comprises first and second variable delay circuits controlled by the processor.

13. The apparatus of claim 12, wherein the first and second variable delay circuits receive digital inputs from the processor selecting the amount of delay time at turn-on and turn-off of said one of said switches.

14. The apparatus of claim 4, wherein the processor comprises any one of a digital signal processor, microprocessor, microcontroller or logic circuit.

15. The apparatus of claim 1, wherein the selected parameter comprises the duty cycle of a pulse width modulated control signal adapted to drive a control terminal of at least one of the switches.

16. The apparatus of claim 1, wherein the control arrangement changes the dead time by changing a variable turn-off delay and monitors the selected parameter after the change to determine if the power loss is smaller, and if it is smaller, implements the turn-off delay, and if the power loss is not smaller, restores the previous turn-off delay.

17. The apparatus of claim 1, wherein the control arrangement changes the dead time by changing a variable turn-on delay and monitors the selected parameter after the change to determine if the power loss is smaller, and if it is smaller, implements the turn-on delay, and if the power loss is not smaller, restores the previous turn-on delay.

18. The apparatus of claim 17, wherein the control arrangement changes the dead time by changing a variable turn-off delay and monitors the selected parameter after the change to determine if the power loss is smaller, and if it is smaller, implements the turn-off delay, and if the power loss is not smaller, restores the previous turn-off delay.

19. The apparatus of claim 18, wherein the control arrangement transmits respective first and second signals to the dead time implementing stage to select a turn-off delay and a turn-on delay of a control signal to one of the switches before the control signal for the control of the other of the switches is turned on and off, respectively.

20. The apparatus of claim 19, further comprising a fixed delay stage for delaying the control signal for the control of the other of the switches.

21. The apparatus of claim 20, wherein the fixed delay stage allows the dead time implementing stage to implement positive and negative amounts of dead time.

22. The apparatus of claim 1, wherein the control arrangement monitors the selected parameter for a plurality of times before setting the change in dead time to improve reliability when the power supply is exposed to fast load transients.

23. The apparatus of claim 1, wherein the control arrangement comprises any one of a digital signal processor, microprocessor, microcontroller or logic circuit.

24. The apparatus of claim 1, wherein the control arrangement comprises a logic magnitude comparator for comparing power loss.

25. The apparatus of claim 1, when the two switches comprise semi-conductor switches.

26. The apparatus of claim 25, where the two switches comprise MOSFETs.

27. A method for minimizing power losses associated with dead time between ON times of two series connected switches of a power converter connected across a supply potential, the method comprising:

monitoring a selected parameter associated with power loss during the dead time of the converter;

comparing power losses associated with the selected parameter for selected instants in time corresponding to a first dead time and a second, changed dead time and determining which of the power losses corresponding to the two dead times is smaller;

selecting the dead time associated with the smaller power loss; and

setting the dead time to the selected dead time.

28. The method of claim 27, where the step of setting the dead time comprises implementing a variable turn-off of a control signal to one of the switches and a variable turn-on of the control signal to said one of the switches.

29. The method of claim 28, wherein the steps of implementing a variable turn-off and a variable turn-on comprises using first and second variable delay stages.

30. The method of claim 27, wherein the selected parameter comprises the duty cycle of a pulse width modulated control signal adapted to drive a control terminal of at least one of the switches.

31. The method of claim 30, wherein the step of monitoring comprises sampling the pulse width modulated signal at the selected instants in time corresponding to the first and second dead times.

32. The method of claim 31, wherein the step of comparing comprises comparing first and second time delayed samples of said pulse width modulated signal and determining which of the samples is associated with a smaller power loss.

33. The method of claim 32, wherein a reduced duty cycle is associated with a smaller power loss.

34. The method of claim 32, further comprising modulating the supply potential with said pulse width modulated signal to produce a signal proportional to the duty cycle of the pulse width modulated signal.

35. The method of claim 34, wherein the step of modulating comprises multiplying the supply potential with the pulse width modulated signal.

36. The method of claim 34, further comprising low pass filtering said signal proportional to the duty cycle to a filtered signal corresponding to the output voltage of the converter if there were no converter losses.

37. The method of claim 27, wherein the one of the switches performs a synchronous rectification function and the other switch is a control switch.

38. The method of claim 27, wherein the steps of selecting and setting comprise changing the dead time by changing a variable turn-off delay and monitoring the selected parameter after the change to determine if the power loss is smaller, and if it is smaller, implementing the turn-off delay, and if the power loss is not smaller, restoring the previous turn-off delay.

39. The method of claim 27, wherein the steps of selecting and setting comprise changing the dead time by changing a variable turn-on delay and monitoring the selected parameter after the change to determine if the power loss is smaller, and if it is smaller, implementing the turn-on delay, and if the power loss is not smaller, restoring the previous turn-on delay.

40. The method of claim 39, wherein the steps of selecting and setting comprise changing the dead time by changing a variable turn-off delay and monitoring the selected parameter after the change to determine if the power loss is smaller, and if it is smaller, implementing the turn-off delay, and if the power loss is not smaller, restoring the previous turn-off delay.

41. The method of claim 39, further comprising transmitting respective first and second signals to a variable delay stage to select a turn-off delay and a turn-on delay before the control signal for the control of the other of the switches is turned on and off, respectively.

42. The method of claim 41, further comprising delaying the control signal for the control of the other of the switches.

43. The method of claim 42, further comprising causing the variable delay stage to implement positive and negative amounts of dead time.

44. The method of claim 27, further comprising monitoring the selected parameter for a plurality of times before setting the change in dead time to improve reliability when the power supply is exposed to fast load transients.

45. The method of claim 27, wherein the steps of monitoring, comparing, selecting and setting are performed by any one of a digital signal processor, microprocessor, microcontroller or logic circuit.

46. The method of claim 27, wherein the steps of selecting and setting are performed by any one of a digital signal processor, microprocessor, microcontroller or logic circuit.

47. The method of claim 27, when the two switches comprise

semiconductor switches.

48. The method of claim 47, wherein the semiconductor switches comprise MOSFETs.

49. A method of minimizing power losses associated with the dead time between ON times of two series-connected switches of a power converter connected across a supply potential and having a switched node between the switches, the method comprising:

establishing a first dead time;

monitoring a parameter associated with power loss during the dead time;

determining a measure of power loss associated with the first dead time;

changing the dead time to a second dead time;

determining a measure of power loss associated with the second dead time;

comparing the measures of power loss for the first and second dead times;

determining which measure of power loss is less; and

setting the dead time to the first or second dead time associated with the lower power loss.

50. The method of claim 49, wherein the step of changing the dead time includes both decreasing the dead time and increasing the dead time.

51. The method of claim 49, further comprising performing each of said recited steps a plurality of times and determining if the second dead time results in a lower power loss for a majority of said times, and if so, setting the dead time to the second dead time, and if not, restoring the first dead time.

52. The method of claim 49, wherein the step of changing the dead time comprises changing the turn-off time of a control signal to one of said switches.

53. The method of claim 49, wherein the step of changing the dead time comprises changing the turn-on time of a control signal to one of said switches.

54. The method of claim 49, wherein the step of changing the dead time comprises changing the turn-off time and the turn-on time of a control signal to one of said switches.

55. The method of claim 54 wherein the one of said switches performs synchronous rectification.

56. The method of claim 55, further comprising delaying a second control signal to a second of said switches acting as a control switch.

57. The method of claim 49, wherein said switches each comprises a MOSFET.

58. The method of claim 49, wherein the step of monitoring a parameter comprises monitoring the duty cycle of a pulse width modulated control signal supplied to at least one of said switches.

59. The method of claim 58, wherein when a dead time is set that results in a lower power loss, the duty cycle is decreased.