Radio receiver, system on a chip integrated circuit and methods for use therewith
First Claim
1. A radio receiver comprising:
- an analog front end for receiving a received radio signal containing a selected one of a plurality of channel signals, and for converting the selected one of the plurality of channel signals into a digital signal;
a digital clock generator, for generating a base clock signal at a base clock frequency that varies based on the selected one of the plurality of channel signals and for generating a first digital clock signal having a substantially constant number of first digital clock cycles over a predetermined period and for generating a second digital clock signal having a substantially constant number of second digital clock cycles over the predetermined period; and
a digital section, operably coupled to the analog front end and the digital clock generator, for converting the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channels, the digital section having a first digital module that operates based on the first digital clock signal and a second digital module that operates based on the second digital clock signal.
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Accused Products
Abstract
A system on a chip integrated circuit includes a first digital module a second digital module such that the first digital module and the second digital module are operably coupled to generate an output signal based on an input signal, based on the first digital clock signal and the second digital clock signal. A digital clock generator generates a base clock signal at a base clock frequency that varies based on a control signal and generates a first digital clock signal having a substantially constant number of first digital clock cycles over a predetermined period and for generating a second digital clock signal having a substantially constant number of second digital clock cycles over the predetermined period.
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Citations
34 Claims
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1. A radio receiver comprising:
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an analog front end for receiving a received radio signal containing a selected one of a plurality of channel signals, and for converting the selected one of the plurality of channel signals into a digital signal; a digital clock generator, for generating a base clock signal at a base clock frequency that varies based on the selected one of the plurality of channel signals and for generating a first digital clock signal having a substantially constant number of first digital clock cycles over a predetermined period and for generating a second digital clock signal having a substantially constant number of second digital clock cycles over the predetermined period; and a digital section, operably coupled to the analog front end and the digital clock generator, for converting the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channels, the digital section having a first digital module that operates based on the first digital clock signal and a second digital module that operates based on the second digital clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A system on a chip integrated circuit comprising:
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a first digital module; a second digital module; and a digital clock generator, operably coupled to the first digital module and the second digital module, for generating a base clock signal at a base clock frequency that varies based on a control signal and for generating a first digital clock signal having a substantially constant number of first digital clock cycles over a predetermined period and for generating a second digital clock signal having a substantially constant number of second digital clock cycles over the predetermined period; wherein the first digital module and the second digital module are operably coupled to generate an output signal based on an input signal, based on the first digital clock signal and the second digital clock signal. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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21. A method comprising:
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generating a base clock signal at a base clock frequency that varies based on a control signal; producing a first stall signal and a second stall signal in response to a first value of the control signal; generating a first digital clock signal having a substantially constant number of first digital clock cycles over a predetermined period by selectively inserting at least one stall cycle in response to the first stall signal; and generating a second digital clock signal having a substantially constant number of second digital clock cycles over the predetermined period by selectively inserting at least one stall cycle in response to the second stall signal. - View Dependent Claims (22, 23, 24, 25)
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26. An integrated circuit comprising:
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a first digital module; a second digital module; and a digital clock generator, operably coupled to the first digital module and the second digital module, for generating a base clock signal at a base clock frequency that varies based on a control signal and for generating a first digital clock signal having a number of first digital clock cycles over a predetermined period and for generating a second digital clock signal having a number of second digital clock cycles over the predetermined period, wherein the number of first digital clock cycles and the number of second digital clock cycles are distributed substantially uniformly over the predetermined period; wherein the first digital module and the second digital module are operably coupled to generate an output signal based on an input signal, based on the first digital clock signal and the second digital clock signal. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34)
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Specification