Method and system for power factor correction using constant pulse proportional current
First Claim
1. A system for improving the power factor to near unity between a low frequency AC power source and a complex load, the system comprising:
- a bridge rectifier circuit having an input disposed to be operatively connected to the AC power source to convert an AC power source voltage signal therefrom into a low frequency fully rectified voltage signal at an output of the bridge rectifier circuit;
a boost converter unit having an input operatively connected to the output of the bridge rectifier circuit to receive and convert the low frequency fully rectified voltage signal into a DC voltage disposed to be applied across the complex load at an output of the boost converter; and
a high frequency controller circuit operatively connected between a control input of the boost converter unit and a negative terminal of the output of the boost converter unit includes a pulse width modulation circuit to generate a control signal having trains of pulses, constant in frequency and duty cycle during a time period equal to or longer than one semi-cycle period of the AC power source voltage signal to be provided to the control input of the boost converter unit so a current amount absorbed by the boost converter unit from the AC power source is contingent and linearly proportional to the AC power source voltage signal wherein the pulse width modulation circuit includes a voltage ramp buffer sub-circuit to compare and amplify the control signal to a reference voltage.
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Accused Products
Abstract
A Power Factor Correction (PFC) system providing near unity power factor for an AC power source (VAC) connected to a complex load. The system includes a bridge rectifier, boost or buck-boost converter, complex load, and pulse width modulation (PWM) controller to provide pulses with variable duty cycle to a power switch. The invention is a constant pulse proportional current (CPPC) PWM controller that generates trains of pulses constant in frequency and duty cycle for one semi-cycle of the VAC. The duty cycle of the driving signal is modified by applying open-loop correction signals to summing nodes of PWM circuits. Since the PWM provides a constant train of driving pulses with constant duty cycle for one semi-cycle of the VAC, the current absorbed by the converter is contingent and linearly proportional to the voltage. Thus, the output current follows the voltage resulting in a power factor of near unity.
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Citations
26 Claims
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1. A system for improving the power factor to near unity between a low frequency AC power source and a complex load, the system comprising:
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a bridge rectifier circuit having an input disposed to be operatively connected to the AC power source to convert an AC power source voltage signal therefrom into a low frequency fully rectified voltage signal at an output of the bridge rectifier circuit; a boost converter unit having an input operatively connected to the output of the bridge rectifier circuit to receive and convert the low frequency fully rectified voltage signal into a DC voltage disposed to be applied across the complex load at an output of the boost converter; and a high frequency controller circuit operatively connected between a control input of the boost converter unit and a negative terminal of the output of the boost converter unit includes a pulse width modulation circuit to generate a control signal having trains of pulses, constant in frequency and duty cycle during a time period equal to or longer than one semi-cycle period of the AC power source voltage signal to be provided to the control input of the boost converter unit so a current amount absorbed by the boost converter unit from the AC power source is contingent and linearly proportional to the AC power source voltage signal wherein the pulse width modulation circuit includes a voltage ramp buffer sub-circuit to compare and amplify the control signal to a reference voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A system for improving the power factor to near unity between a low frequency AC power source and a complex load, the system comprising:
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a bridge rectifier circuit operatively connected to the AC power source to convert an AC voltage into a low frequency fully rectified voltage signal; one of a buck-boost and flyback converter unit operatively connected to the bridge rectifier to receive and convert the low frequency fully rectified signal into a DC voltage across the complex load; a high frequency controller circuit operatively connected between a control input of the one of the buck-boost and flyback converter and a negative terminal of the output of the one of the buck-boost and flyback converter, wherein the high frequency controller circuit includes a pulse width modulation circuit to generate a control signal having trains of pulses, constant in frequency and duty cycle during a time period equal to or longer than one semi-cycle period of the AC power source signal to be applied to the control input of the one of the buck-boost and flyback converter so that the current amount absorbed by the one of the buck-boost and flyback converter from the AC power source is contingent and linearly proportional to the AC power source voltage signal wherein the pulse width modulation circuit includes a voltage ramp buffer sub-circuit to compare and amplify the control signal to a reference voltage. - View Dependent Claims (20, 21)
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22. A method of power factor correction with a constant pulse proportional current mode of operation between an applied low frequency AC power signal and a complex load including a capacitor forming a DC output voltage, the method comprising:
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rectifying the low frequency AC power signal having a peak voltage level to provide a fully rectified supply signal; high frequency converting the fully rectified supply signal into the DC output voltage using a high frequency controllable boost converter; applying the fully rectified supply signal to the capacitor of the complex load; eliminating a direct current component of the fully rectified supply signal from the complex load to maintain a DC voltage component of the fully rectified supply signal across the complex load at a higher voltage level than the AC power signal peak voltage level; controlling the high frequency converting step with driving pulse signals each generated at a period of a selected clock cycle from a constant pulse proportional current pulse width modulation controller consisting of; a voltage ramp buffer sub-circuit comparing and amplifying the fully rectified supply signal generating a voltage ramp correction signal; a voltage error amplifier sub-circuit coupled to the voltage ramp buffer sub-circuit receiving and amplifying the voltage ramp correction signal; and an analog reset switching sub-circuit operatively connected to the voltage error amplifier sub-circuit and voltage ramp buffer sub-circuit for rapidly decreasing the amplified voltage ramp correction signal to near zero during each clock cycle wherein trains of pulses constant in frequency and duty cycle during a time equal to or longer than one semi-cycle period of the AC power signal so that the current absorbed from the AC power signal is contingent and linearly proportional to the AC power signal peak voltage level. - View Dependent Claims (23, 24)
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25. A system for improving the power factor to near unity between a low frequency AC power source and a complex load, the system comprising:
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a bridge rectifier circuit having an input disposed to be operatively connected to the AC power source to convert an AC power source voltage signal therefrom into a low frequency fully rectified voltage signal at an output of the bridge rectifier circuit; a boost converter unit having an input operatively connected to the output of the bridge rectifier circuit to receive and convert the low frequency fully rectified voltage signal into a DC voltage disposed to be applied across the complex load at an output of the boost converter; and a high frequency controller circuit operatively connected between a control input of the boost converter and a negative terminal of the output of the boost converter includes a pulse width modulation circuit to generate a control signal having trains of pulses, constant in frequency and duty cycle during a time period equal to or longer than one semi-cycle period of the AC power source voltage signal to be provided to the control input of the boost converter so a current amount absorbed by the boost converter from the AC power source is contingent and linearly proportional to the AC power source voltage signal wherein the pulse width modulation circuit includes; a fixed frequency oscillator sub-circuit to generate a set logic output, a reset logic output, a clock logic output, and a voltage ramp output signal as synchronizing signals; a voltage error amplifier sub-circuit disposed to receive and amplify the control signal; and a pulse width modulation logic sub-circuit having inputs from the fixed frequency oscillator and voltage error amplifier sub-circuits to generate a driving signal with a duty cycle contingent and proportional to the inputs.
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26. A method of power factor correction with a constant pulse proportional current mode of operation between an applied low frequency AC power signal and a complex load including a capacitor forming a DC output voltage, the method comprising:
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rectifying the low frequency AC power signal having a peak voltage level to provide a fully rectified supply signal and control signal; high frequency converting the fully rectified supply signal into the DC output voltage using one of a high frequency controllable buck-boost converter and a flyback converter; applying the fully rectified supply signal to the capacitor of the complex load; eliminating a direct current component of the fully rectified supply signal from the complex load to maintain a DC voltage component of the fully rectified supply signal across the complex load; controlling the high frequency converting step with driving pulse signals each generated at a period of a selected clock cycle from a constant pulse proportional current pulse width modulation controller consisting of; a voltage ramp buffer sub-circuit comparing and amplifying the fully rectified supply signal generating a voltage ramp correction signal; a voltage error amplifier sub-circuit coupled to the voltage ramp buffer sub-circuit receiving and amplifying the voltage ramp correction signal; and an analog reset switching sub-circuit operatively connected to the voltage error amplifier sub-circuit and voltage ramp buffer sub-circuit for rapidly decreasing the amplified voltage ramp correction signal to near zero during each clock cycle wherein trains of pulses constant in frequency and duty cycle during a time equal to or longer than one semi-cycle period of the AC power signal so the current absorbed from the AC power signal is contingent and linearly proportional to the AC power signal peak voltage level.
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Specification