Method and system for power factor correction using constant pulse proportional current

• US 7,391,630 B2
• Filed: 10/25/2004
• Issued: 06/24/2008
• Est. Priority Date: 10/24/2003
• Status: Expired due to Fees

• Current Assignee: Alterlume, Inc., Joseph Durante, PF1 Incorporated, Power Factor 1
• Original Assignee: PF1 Incorporated
• Inventors: Acatrinei, Benjamin
• Primary Examiner(s): Sterrett; Jeffrey L
• Application Number:
  US10/973,748
• Publication Number:
  US 20050212501A1
• Time in Patent Office: 1,338 Days
• Field of Search: 363/89
• US Class Current: 363/89
• CPC Class Codes: G05F 1/70 Regulating power factor; Regulating reactive current or power
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 1/4208 Arrangements for improving power factor of AC input
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A Power Factor Correction (PFC) system providing near unity power factor for an AC power source (VAC) connected to a complex load. The system includes a bridge rectifier, boost or buck-boost converter, complex load, and pulse width modulation (PWM) controller to provide pulses with variable duty cycle to a power switch. The invention is a constant pulse proportional current (CPPC) PWM controller that generates trains of pulses constant in frequency and duty cycle for one semi-cycle of the VAC. The duty cycle of the driving signal is modified by applying open-loop correction signals to summing nodes of PWM circuits. Since the PWM provides a constant train of driving pulses with constant duty cycle for one semi-cycle of the VAC, the current absorbed by the converter is contingent and linearly proportional to the voltage. Thus, the output current follows the voltage resulting in a power factor of near unity.

Claims

1. A system for improving the power factor to near unity between a low frequency AC power source and a complex load, the system comprising:

a bridge rectifier circuit having an input disposed to be operatively connected to the AC power source to convert an AC power source voltage signal therefrom into a low frequency fully rectified voltage signal at an output of the bridge rectifier circuit;

a boost converter unit having an input operatively connected to the output of the bridge rectifier circuit to receive and convert the low frequency fully rectified voltage signal into a DC voltage disposed to be applied across the complex load at an output of the boost converter; and

a high frequency controller circuit operatively connected between a control input of the boost converter unit and a negative terminal of the output of the boost converter unit includes a pulse width modulation circuit to generate a control signal having trains of pulses, constant in frequency and duty cycle during a time period equal to or longer than one semi-cycle period of the AC power source voltage signal to be provided to the control input of the boost converter unit so a current amount absorbed by the boost converter unit from the AC power source is contingent and linearly proportional to the AC power source voltage signal wherein the pulse width modulation circuit includes a voltage ramp buffer sub-circuit to compare and amplify the control signal to a reference voltage.

2. A system as in claim 1 wherein the boost converter unit comprises:

a capacitive circuit coupled across the output of the bridge rectifier circuit to present a high impedance in respect to the AC power source low frequency supply signal and low impedance in respect to a boost converter high frequency signal;

a high frequency rectifier diode having an anode and a cathode with the cathode coupled to a positive terminal of the output of the boost converter;

an oscillating inductor having a first end coupled to a positive terminal of the output of the bridge rectifier circuit and a second end coupled to the anode of the high frequency rectifier diode, wherein the inductor has associated therewith a charging time and a discharging time; and

a controllable power switch circuit with one end coupled to a junction of the second end of the oscillating inductor and the anode of the high frequency rectifier diode and an other end coupled to a negative terminal of the output of the bridge rectifier circuit for periodically charging the oscillating inductor.

3. A system of claim 1 when operating in a voltage control mode said boost converter unit creates a correction signal or plurality of signals from the fully rectified voltage signal or DC voltage across the complex load and adjustment of the duty cycle of the driving signal from the pulse width modulation circuit includes altering a first voltage with a portion of a second voltage and proportionally altering the pulse duty cycle of the driving signal.

4. A system of claim 1 wherein when operating in current control mode said boost converter unit creates a correction voltage signal from a voltage drop across a sense resistor between the power switch and ground or from a voltage drop across a sense resistor to ground between the boost converter unit and a negative terminal of the bridge rectifier circuit;

wherein adjustment of the duty cycle of the driving signal from the pulse width modulation circuit includes altering a first correction voltage with a portion of a second correction voltage and proportionally altering the pulse duty cycle of the driving signal.

5. A system as in claim 1 wherein said pulse width modulation circuit further includes:

a voltage error amplifier sub-circuit coupled to the voltage ramp buffer sub-circuit to receive and amplify the control signal; and

an analog reset switching sub-circuit operatively connected to the voltage error amplifier sub-circuit input and voltage ramp buffer sub-circuit output to rapidly decrease a voltage ramp signal to near zero during each clock cycle.

6. A system as in claim 1 where the high frequency controller circuit is a constant pulse proportional current controller circuit.

7. A system as in claim 6 where the control signals are are effectively open loop correction signals comprised of one of the following:

a voltage signal formed by a first resistive divider circuit of the fully rectified signal;

a voltage signal formed by a second resistive divider circuit of the DC voltage across the complex load; and

a voltage signal from a sense resistor between the controllable power switch and the negative terminal of the bridge rectifier circuit.

8. A system of claim 7 wherein the high frequency controller circuit is a digital constant pulse proportional current controller circuit comprises:

a digital pulse width modulation circuit to generate the trains of pulses, constant in frequency and duty cycle during a time equal to or longer than one semi-cycle period of the AC power source; and

summing nodes for injecting control signal into the pulse width modulator circuit.

9. A system as in claim 7:

wherein the pulse width modulation circuit includes input and output terminals disposed to receive operating voltage, to be connected to ground, to receive control signals and to provide an output driving signal;

the pulse width modulation circuit further comprises;

an internal supply and protection sub-circuit disposed to receive an input voltage to provide a standard voltage to the pulse width modulation sub-circuits and to provide protection and shutdown functions;

a voltage reference sub-circuit disposed to be connected to ground and to provide precision voltage references to other sub-circuits;

a fixed frequency oscillator sub-circuit to generate a set logic output, a reset logic output, a clock logic output, and voltage ramp output signals as synchronizing signals to other sub-circuits;

a voltage limiter sub-circuit having a resistive-diode divider network to limit the compensation voltage and provide a feedback signal to one input of a voltage error amplifier sub-Circuit;

the voltage error amplifier sub-circuit coupled to the voltage limiter sub-circuit and disposed to receive the control signal to amplify the correction signal and cause a pulse width modulation logic sub-circuit to modify the duty cycle of the driving signal to the power switch;

an analog reset switching sub-circuit operatively connected to the voltage error amplifier sub-circuit input and voltage ramp buffer sub-circuit output to rapidly decrease the voltage ramp signal to near zero during each clock cycle;

the pulse width modulation logic sub-circuit having input signals from the fixed frequency oscillator and voltage error amplifier sub-circuits to generate a driving signal with a duty cycle contingent with, and proportional to, the input signals;

a soft start sub-circuit to delay reference voltages and other sub-circuit operations to ensure smooth startup of the pulse width modulator circuit; and

a start enforcer sub-circuit to delay operation of the voltage error amplifier sub-circuit at startup to prevent large duty cycles and unsafe startup operation.

10. A system as in claim 9 further comprises an error amplifier comprising:

an input connected to an output of the voltage ramp buffer sub-circuit and connected to the analog reset switching sub-circuit to receive the correction signal;

an input connected to an output of the voltage limiter sub-circuit to receive the correction signal; and

an output of the error amplifier sub-circuit is a summing node of the input correction signals from the voltage ramp buffer sub-circuit and the voltage limiter sub-circuit.

11. A system of claim 9 of a voltage ramp buffer sub-circuit comprises:

a first input terminal to receive voltage ramp signals from the fixed frequency oscillator sub-circuit;

a second input terminal to receive an injected open-loop correction input signal;

a third input terminal to receive a voltage reference input signal; and

a resistive output forming a summing node and amplifying the oscillator voltage ramp signal with the injected open-loop correction input signal coupled to drive one input of the voltage error amplifier sub-circuit.

12. A system of claim 9 further comprising an analog reset switching sub-circuit to periodically sense the state of the pulse width modulation logic sub-circuit and force the input of the error amplifier sub-circuit from the voltage ramp buffer sub-circuit to zero wherein the pulse width modulation logic sub-circuit is reset to its initial state within one clock cycle of the oscillator sub-circuit the analog reset switching sub-circuit includes:

an input to receive a signal from the pulse width modulation logic sub-circuit output; and

a low-side output connected to the input of the voltage error amplifier sub-circuit and to the output of the voltage ramp buffer sub-circuit.

13. A system of claim 6, wherein the high frequency controller circuit is a digital constant pulse proportional current controller circuit comprises:

a digital pulse width modulation circuit to generate the trains of pulses, constant in frequency and duty cycle during a time equal to or longer than one semi-cycle period of the AC power source; and

summing nodes for injecting control signal into the pulse width modulator circuit.

14. A power factor correction system of claim 13:

further comprises a digital pulse width modulation logic block; and

wherein said summing nodes are within a control loop for injecting correction signals into said digital pulse width modulation logic block to modify the duty cycle of the driving pulse signal to the power switch.

15. A power factor correction system of claim 14 wherein the constant pulse proportional current controller is a digital constant pulse proportional current controller wherein the open-loop correction signals are much faster than the bandwidth of the pulse width modulation control loop and may be inserted and not cancelled by the pulse width modulation control loop, effectively making them open loop correction signals.

16. A power factor correction system of claim 14 further comprises a digital constant pulse proportional controller circuit operating as one of a buck-boost converter and a fly back converter.

17. A power factor correction system of claim 14 wherein operation is in a voltage control mode.

18. A power factor correction system of claim 14 wherein operation is in a current control mode.

19. A system for improving the power factor to near unity between a low frequency AC power source and a complex load, the system comprising:

a bridge rectifier circuit operatively connected to the AC power source to convert an AC voltage into a low frequency fully rectified voltage signal;

one of a buck-boost and flyback converter unit operatively connected to the bridge rectifier to receive and convert the low frequency fully rectified signal into a DC voltage across the complex load;

a high frequency controller circuit operatively connected between a control input of the one of the buck-boost and flyback converter and a negative terminal of the output of the one of the buck-boost and flyback converter, wherein the high frequency controller circuit includes a pulse width modulation circuit to generate a control signal having trains of pulses, constant in frequency and duty cycle during a time period equal to or longer than one semi-cycle period of the AC power source signal to be applied to the control input of the one of the buck-boost and flyback converter so that the current amount absorbed by the one of the buck-boost and flyback converter from the AC power source is contingent and linearly proportional to the AC power source voltage signal wherein the pulse width modulation circuit includes a voltage ramp buffer sub-circuit to compare and amplify the control signal to a reference voltage.

20. A system of claim 19 where the one of the buck-boost and flyback converter comprises:

a capacitive circuit coupled across the output terminals of the rectifier bridge circuit to present a high impedance in respect to that of the AC power source low frequency supply signal and a low impedance in respect to that of the one of the buck-boost and flyback converter high frequency signal;

a high frequency rectifier diode coupled to the complex load, wherein the high frequency rectifier diode includes;

a power switch anode; and

a cathode, wherein the cathode of the high frequency rectifier diode is coupled to a positive end of the complex load;

an oscillating inductor having;

a primary inductor winding coupled between a positive output terminal of the output terminals of the bridge rectifier circuit and the power switch anode of the high frequency rectifier diode, wherein the primary inductor defines a first charging time and a first discharging time;

a secondary inductor winding coupled between the anode of a high frequency rectifier diode and a ground terminal, wherein the secondary inductor winding defines a second charging time and a second discharging time; and

a controllable power switch circuit coupled between the primary inductor winding and a sense resistor connected to a negative terminal of the output terminals of the bridge rectifier circuit for periodically charging the oscillating inductor and a control terminal of the controllable power switch circuit operatively disposed to receive the control signal.

21. A system of claim 19 when the one of the buck-boost and flyback converter is operating in voltage control mode a correction signal or plurality of signals is created from a fully rectified voltage from the bridge rectifier circuit or a DC voltage across the complex load, wherein steps of adjusting the duty cycle of the driving signal from the pulse width modulation circuit include altering a first voltage with a portion of a second voltage and proportionally altering the driving pulse duty cycle.

22. A method of power factor correction with a constant pulse proportional current mode of operation between an applied low frequency AC power signal and a complex load including a capacitor forming a DC output voltage, the method comprising:

rectifying the low frequency AC power signal having a peak voltage level to provide a fully rectified supply signal;

high frequency converting the fully rectified supply signal into the DC output voltage using a high frequency controllable boost converter;

applying the fully rectified supply signal to the capacitor of the complex load;

eliminating a direct current component of the fully rectified supply signal from the complex load to maintain a DC voltage component of the fully rectified supply signal across the complex load at a higher voltage level than the AC power signal peak voltage level;

controlling the high frequency converting step with driving pulse signals each generated at a period of a selected clock cycle from a constant pulse proportional current pulse width modulation controller consisting of;

a voltage ramp buffer sub-circuit comparing and amplifying the fully rectified supply signal generating a voltage ramp correction signal;

a voltage error amplifier sub-circuit coupled to the voltage ramp buffer sub-circuit receiving and amplifying the voltage ramp correction signal; and

an analog reset switching sub-circuit operatively connected to the voltage error amplifier sub-circuit and voltage ramp buffer sub-circuit for rapidly decreasing the amplified voltage ramp correction signal to near zero during each clock cycle wherein trains of pulses constant in frequency and duty cycle during a time equal to or longer than one semi-cycle period of the AC power signal so that the current absorbed from the AC power signal is contingent and linearly proportional to the AC power signal peak voltage level.

23. A method of claim 22 wherein the constant pulse proportional current pulse width modulation controller forms a control loop between the complex load and the boost converter, the steps comprised of:

applying the fully rectified signal as an open-loop control signal to the voltage ramp buffer sub-circuit of the pulse width modulation controller;

applying an output voltage from the complex load as an open-loop control signal to the voltage error amplifier sub-circuit for modifying the driving pulse signals of the pulse width modulation controller and compensating the control loop;

applying a sense voltage coupled from a sense resistor between a power switch of the boost converter and ground as an open-loop control signal to the voltage ramp buffer sub-circuit of the pulse width modulation controller providing a current limiting control loop;

summing open-loop control signals within the constant pulse proportional current pulse width modulation controller;

generating a train of pulses from the pulse width modulation controller constant in frequency and duty cycle during a time equal to or longer than one semi-cycle period of the AC power signal to drive the power switch.

24. A method of claim 22 wherein the constant pulse proportional current pulse width modulation controller is implemented with mixed signal circuits, analog circuits only or digital circuits only.

25. A system for improving the power factor to near unity between a low frequency AC power source and a complex load, the system comprising:

a bridge rectifier circuit having an input disposed to be operatively connected to the AC power source to convert an AC power source voltage signal therefrom into a low frequency fully rectified voltage signal at an output of the bridge rectifier circuit;

a boost converter unit having an input operatively connected to the output of the bridge rectifier circuit to receive and convert the low frequency fully rectified voltage signal into a DC voltage disposed to be applied across the complex load at an output of the boost converter; and

a high frequency controller circuit operatively connected between a control input of the boost converter and a negative terminal of the output of the boost converter includes a pulse width modulation circuit to generate a control signal having trains of pulses, constant in frequency and duty cycle during a time period equal to or longer than one semi-cycle period of the AC power source voltage signal to be provided to the control input of the boost converter so a current amount absorbed by the boost converter from the AC power source is contingent and linearly proportional to the AC power source voltage signal wherein the pulse width modulation circuit includes;

a fixed frequency oscillator sub-circuit to generate a set logic output, a reset logic output, a clock logic output, and a voltage ramp output signal as synchronizing signals;

a voltage error amplifier sub-circuit disposed to receive and amplify the control signal; and

a pulse width modulation logic sub-circuit having inputs from the fixed frequency oscillator and voltage error amplifier sub-circuits to generate a driving signal with a duty cycle contingent and proportional to the inputs.

26. A method of power factor correction with a constant pulse proportional current mode of operation between an applied low frequency AC power signal and a complex load including a capacitor forming a DC output voltage, the method comprising:

rectifying the low frequency AC power signal having a peak voltage level to provide a fully rectified supply signal and control signal;

high frequency converting the fully rectified supply signal into the DC output voltage using one of a high frequency controllable buck-boost converter and a flyback converter;

applying the fully rectified supply signal to the capacitor of the complex load;

eliminating a direct current component of the fully rectified supply signal from the complex load to maintain a DC voltage component of the fully rectified supply signal across the complex load;

controlling the high frequency converting step with driving pulse signals each generated at a period of a selected clock cycle from a constant pulse proportional current pulse width modulation controller consisting of;

a voltage ramp buffer sub-circuit comparing and amplifying the fully rectified supply signal generating a voltage ramp correction signal;

a voltage error amplifier sub-circuit coupled to the voltage ramp buffer sub-circuit receiving and amplifying the voltage ramp correction signal; and

an analog reset switching sub-circuit operatively connected to the voltage error amplifier sub-circuit and voltage ramp buffer sub-circuit for rapidly decreasing the amplified voltage ramp correction signal to near zero during each clock cycle wherein trains of pulses constant in frequency and duty cycle during a time equal to or longer than one semi-cycle period of the AC power signal so the current absorbed from the AC power signal is contingent and linearly proportional to the AC power signal peak voltage level.