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Memory device and method for reading data

  • US 7,391,639 B2
  • Filed: 02/14/2006
  • Issued: 06/24/2008
  • Est. Priority Date: 02/14/2006
  • Status: Active Grant
First Claim
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1. A memory apparatus, comprising:

  • a plurality of memory cells, wherein each memory cell is connected with a common plate line supplying a plate voltage and with one of a plurality of bit lines, wherein each memory cell comprises;

    a resistive element having a programmable resistance and having a first terminal coupled to the common plate line; and

    a cell switch comprising a control input coupled to a word line for controlling a switching state of the cell switch, wherein the cell switch couples a second end of the resistive element to a respectively coupled bit line when switched-on;

    a first bit line of a bit line pair connectable to a first voltage level;

    a second bit line of the bit line pair connectable to a second voltage level, wherein the second voltage level is between the plate voltage level and the first voltage level; and

    a sense amplifier connectable to the first and second bit lines and amplifying a voltage difference between the first and second bit lines.

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