Memory device and method for reading data

• US 7,391,639 B2
• Filed: 02/14/2006
• Issued: 06/24/2008
• Est. Priority Date: 02/14/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Infineon Technologies AG
• Inventors: Gogl, Dietmar
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US11/354,281
• Publication Number:
  US 20070189059A1
• Time in Patent Office: 861 Days
• Field of Search: 365/148, 365/163, 365/205, 365/185.25
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/04 using optical elements ; using other beam accessed elements, e.g. electron or ion beam
• CPC Class Codes: G11C 2013/0042 Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A memory with memory cells, wherein a memory cell includes a resistive element and a switch, wherein the memory cells are connected with a common plate line and with respective bit lines, wherein the common plate line supplies a plate voltage, wherein the switches include control inputs that are connected with word lines for controlling the switching states, wherein the word lines are connected with a word line driver that supplies selected word lines with a voltage, wherein the bit lines are connected with second switches, wherein the first bit lines are connectable by respective second switches with a first voltage level and the second bit lines are connectable by respective second switches with a second voltage level, wherein a first and a second bit line are connectable as a bit line pair with a sense amplifier, wherein the sense amplifier amplifies a voltage difference between the first and the second bit line of the bit line pair, wherein the resistive element is able to change the resistance depending on an electrical voltage that is applied across the resistive element, and wherein the second voltage level is between the plate voltage level and the first voltage level.

Claims

1. A memory apparatus, comprising:

a plurality of memory cells, wherein each memory cell is connected with a common plate line supplying a plate voltage and with one of a plurality of bit lines, wherein each memory cell comprises;

a resistive element having a programmable resistance and having a first terminal coupled to the common plate line; and

a cell switch comprising a control input coupled to a word line for controlling a switching state of the cell switch, wherein the cell switch couples a second end of the resistive element to a respectively coupled bit line when switched-on;

a first bit line of a bit line pair connectable to a first voltage level;

a second bit line of the bit line pair connectable to a second voltage level, wherein the second voltage level is between the plate voltage level and the first voltage level; and

a sense amplifier connectable to the first and second bit lines and amplifying a voltage difference between the first and second bit lines.

2. The apparatus of claim 1, wherein the sense amplifier comprises a first input and a second input respectively coupled to the first and second bit lines, wherein the sense amplifier provides an output signal based on the voltage difference between the first and second bit lines, wherein the output signal is transferred to an output of the sense amplifier, and wherein amplified voltages of the first and second inputs are not put back to the first and second bit line.

3. The apparatus of claim 1, further comprising:

a control unit which, when activated, respectively connects the first and second bit lines of the bit line pair to the first and second voltage levels.

4. The apparatus of claim 3, wherein the sense amplifier comprises a first input and a second input respectively coupled to the first and second bit lines, wherein the sense amplifier provides an output signal based on the voltage difference between the first and second bit lines, wherein the output signal is transferred to an output of the sense amplifier, and wherein amplified voltages of the first and second inputs are not put back to the first and second bit line.

5. The apparatus of claim 1, further comprising:

a switch disposed between and controllable to couple the first and second bit lines to one other.

6. The apparatus of claim 5, wherein the sense amplifier comprises a first input and a second input respectively coupled to the first and second bit lines, wherein the sense amplifier provides an output signal based on the voltage difference between the first and second bit lines, wherein the output signal is transferred to an output of the sense amplifier, and wherein amplified voltages of the first and second inputs are not put back to the first and second bit line.

7. The apparatus of claim 1, further comprising:

an amplifier control unit coupled to the sense amplifier and to a column selector for selecting the bit line pair, wherein the amplifier control unit disconnects the first and second bit lines of the bit line pair from the sense amplifier after the sense amplifier has been charged by respective potentials of the first and second bit lines of the bit line pair.

8. The apparatus of claim 7, wherein the sense amplifier is connectable to the first and second bit lines of the bit line pair via a plurality of switches, and wherein the amplifier control unit switches off the plurality of switches when an amplified voltage on at least one of the first bit line and the second bit line deviates from a given voltage range compared to the plate voltage.

9. The apparatus of claim 1, wherein the second voltage level differs from the plate voltage level in a voltage range for reading a program state of the resistive element.

10. The apparatus of claim 1, wherein the resistive element comprises a programmable metallization cell.

11. A method for reading data from a memory cell of a memory device, comprising:

providing the memory cell connected with a common plate line supplying a plate voltage and with a first bit line of a bit line pair, the memory cell comprising;

a resistive element having a resistance which is programmable based on an electrical voltage applied across the resistive element, the resistive element having a first terminal connected to the common plate line; and

a cell switch comprising a control input connected with a word line for controlling a switching state of the cell switch, wherein the cell switch connects a second end of the resistive element to the first bit line when switched-on;

charging the first bit line of the bit line pair to a first voltage level;

charging a second bit line of the bit line pair to a second voltage level, wherein the second voltage level is between the plate voltage level and the first voltage level; and

connecting the first bit line to the memory cell, wherein a voltage level of the first bit line is selectively changed depending on a resistance of the resistive element of the memory cell; and

amplifying a voltage difference between the first bit line and the second bit line of the bit line pair utilizing a sense amplifier connected to the first bit line and the second bit line of the bit line pair.

12. The method of claim 11, further comprising:

precharging the first and the second bit line to a common precharge voltage before respectively charging the first bit line and the second bit line to the first and second voltage levels.

13. The method of claim 11, further comprising:

connecting the first bit line and the second bit line during precharging and during a time period prior to respectively charging the first and the second bit lines to the first and second voltage levels.

14. The method of claim 13, wherein the second voltage level differs from a plate voltage level in a range for reading a program state of the memory cell.

15. A semiconductor memory device, comprising:

a plurality of word lines;

a plurality of bit lines;

a plurality of memory cells, each memory cell comprising;

a programmable resistive cell having a first terminal connected to a plate voltage, the programmable resistive cell having a sensing voltage for reading a resistance value of the programmable resistive cell; and

a cell switch having a control input connected to one of the word lines which, when activated by the connected word line, connects the programmable resistive cell to a first bit line of a bit line pair;

a first switch selectively connecting a first voltage level to the first bit line, wherein the first voltage level is higher than the plate voltage by the sensing voltage;

a second switch selectively connecting a second voltage level to a second bit line of the bit line pair, wherein the second voltage level is between the plate voltage and the first voltage level; and

a sense amplifier connected to the first and second bit lines of the bit line pair, the sense amplifier amplifying a voltage difference between the first bit line and the second bit line of the bit line pair.

16. The semiconductor memory device of claim 15, further comprising:

a control unit selectively activating the cell switch, the first switch and the second switch.

17. The semiconductor memory device of claim 16, further comprising:

a third switch connected between the first and second bit lines, wherein the control unit to switches-on the third switch to equalize the charges on the first and second bit lines in a precharge period before a read operation.

18. The semiconductor memory device of claim 17, wherein the first and second switches are further switchably connect the first and second bit lines to the plate voltage during the precharge period.

19. The semiconductor memory device of claim 15, wherein the second voltage level is halfway between the plate voltage and the first voltage level.