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Non-volatile memory and method with compensation for source line bias errors

  • US 7,391,645 B2
  • Filed: 01/18/2007
  • Issued: 06/24/2008
  • Est. Priority Date: 04/01/2005
  • Status: Expired due to Fees
First Claim
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1. In a non-volatile memory device having individual pages of memory cells to be sensed in parallel, each memory cell having a source, a drain, a charge storage unit and a control gate for controlling a conduction current along said drain and source, a method of sensing a page of memory cells, comprising:

  • providing an aggregate node coupling a source voltage control circuit to the source of each memory cell of said page;

    coupling the drain of each memory cell of said page to an associated bit line; and

    providing a predetermined bit line voltage to the associated bit line of each memory cell of said page for sensing operation, wherein each said predetermined bit line voltage is referenced with respect to said aggregate node so as not to be affected by any voltage differences between the aggregate node and a ground reference.

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