Redundant processing architecture for single fault tolerance
First Claim
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1. A system comprising:
- a first logic device having at least two processors and a first comparator; and
a second logic device having at least one processor and a second comparator;
wherein each of the at least two processors are coupled to each of the first and second comparators;
wherein the first and second comparators operate as a distributed comparator system;
wherein each comparator independently identifies faults in the processors.
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Abstract
An electronic module is provided. The module includes a first logic device having at least two processors and a first comparator and a second logic device having at least one processor and a second comparator. Each of the at least two processors are coupled to each of the first and second comparators. The first and second comparators operate as a distributed comparator system. Each comparator independently identifies faults in the processors.
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Citations
33 Claims
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1. A system comprising:
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a first logic device having at least two processors and a first comparator; and a second logic device having at least one processor and a second comparator; wherein each of the at least two processors are coupled to each of the first and second comparators; wherein the first and second comparators operate as a distributed comparator system; wherein each comparator independently identifies faults in the processors. - View Dependent Claims (2, 3, 4, 5)
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6. A logic device comprising:
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at least three processors that are adapted to perform substantially the same function; at least one hardware comparator comprising; a binary comparator; a control logic device coupled to the binary comparator; a selector coupled to the control logic device; and a broadcaster coupled to the selector; wherein each of the at least three processors includes a software implemented fault tolerance function (SIFT); wherein each of the at least three SIFTs is communicatively coupled to the at least one hardware comparator; and wherein each of the SIFTs operates independently of each other to identify faults in one or more of the at least three processors; wherein the logic device is configured to; perform a first portion of a comparison function using each of the SIFTs; perform a second portion of the comparison function using the hardware comparator; forward results from the second portion of the comparison function to each of the SIFTs; and combine results of each of the first portion of the comparison function and the second portion of the comparison function. - View Dependent Claims (7, 8, 9)
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10. A system comprising:
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a logic device having at least three processors; and at least one hardware comparator coupled to each of the at least three processors, the hardware comparator comprising; a binary comparator; a control logic device coupled to the binary comparator; a selector coupled to the control logic device; and a broadcaster coupled to the selector; wherein each processor includes a software implemented fault tolerance (SIFT) function; wherein the SIFT and the at least one hardware comparator in combination processes outputs of the at least three processors; wherein the SIFT determines if one or more of the at least three processors has failed; wherein the logic device is configured to; perform a first portion of a comparison function using each SIFT; perform a second portion of the comparison function using the hardware comparator; retrieve results of each of the first portion of the comparison function and the second portion of the comparison function; and forward results from the second portion of the comparison function to each SIFT. - View Dependent Claims (11, 12, 13)
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14. A method for identifying a fault in a programmable device having at least three redundant processors each having a software implemented fault tolerance (SIFT) function, the method comprising:
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generating an output at each of the at least three redundant processors; receiving the generated outputs at each of the SIFTs; performing a first portion of a comparison function using each of the SIFTs; performing a second portion of the comparison function using a hardware comparator; forwarding results from the second portion of the comparison function to each of the SIFTs; combining results of each of the first portion of the comparison function and the second portion of the comparison function; and analyzing the combined results, wherein the analysis comprises; performing a voting function of the combined results, comprising checking for a minority vote; and determining faulty processors among the at least three redundant processors based on the minority vote. - View Dependent Claims (15, 16, 17)
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18. A method for accelerating a voting mechanism in a programmable device having at least three redundant processors each having a software implemented fault tolerance (SIFT) function, the method comprising:
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generating an output in each of the at least three redundant processors; receiving the generated outputs at each of the SIFTs; performing a first portion of a comparison function using each of the SIFTs; performing a second portion of the comparison function using a hardware comparator; retrieving results of each of the first portion of the comparison function and the second portion of the comparison function; and forwarding results from the second portion of the comparison function to each of the SIFTs. - View Dependent Claims (19, 20, 21)
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22. An electronic module, comprising:
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a first logic device having at least two processors and a first comparator; and a second logic device having at least one processor and a second comparator; wherein each of the at least two processors are coupled to each of the first and second comparators; wherein the first and second comparators operate as a distributed comparator system; wherein each comparator independently identifies faults in the processors; wherein the logic devices are combined on a single chip. - View Dependent Claims (23, 24, 25, 26)
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27. A machine readable medium having instructions stored thereon for identifying a fault in a programmable device having at least three redundant processors each having a software implemented fault tolerance (SIFT) function, the method comprising:
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generating an output at each of the at least three redundant processors; receiving the generated outputs at each of the SIFTs; performing a first portion of a comparison function using each of the SIFTs; performing a second portion of the comparison function using a hardware comparator; forwarding results from the second portion of the comparison function to each of the SIFTs; combining results of each of the first portion of the comparison function and the second portion of the comparison function; and analyzing the combined results, wherein the analysis comprises; performing a voting of the combined results comprising checking for a minority vote; and determining faulty processors among the at least three redundant processors based on the minority vote. - View Dependent Claims (28, 29)
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30. A machine readable medium having instructions stored thereon for accelerating a voting mechanism in a programmable device having at least three redundant processors each having a software implemented fault tolerance (SIFT) function, the method comprising:
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generating an output in each of the at least three redundant processors; receiving the generated outputs at each of the SIFTs; performing a first portion of a comparison function using each of the SIFTs; performing a second portion of the comparison function using a hardware comparator; retrieving results of each of the first portion of the comparison function and the second portion of the comparison function; and forwarding results from the second portion of the comparison function to each of the SIFTs. - View Dependent Claims (31, 32, 33)
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Specification