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Redundant processing architecture for single fault tolerance

  • US 7,392,426 B2
  • Filed: 06/15/2004
  • Issued: 06/24/2008
  • Est. Priority Date: 06/15/2004
  • Status: Active Grant
First Claim
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1. A system comprising:

  • a first logic device having at least two processors and a first comparator; and

    a second logic device having at least one processor and a second comparator;

    wherein each of the at least two processors are coupled to each of the first and second comparators;

    wherein the first and second comparators operate as a distributed comparator system;

    wherein each comparator independently identifies faults in the processors.

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