Emulation system with peripherals recording emulation frame when stop generated

• US 7,392,431 B2
• Filed: 02/22/2005
• Issued: 06/24/2008
• Est. Priority Date: 02/19/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Swoboda, Gary L.
• Primary Examiner(s): Baderman; Scott T
• Assistant Examiner(s): SCHELL, JOSEPH O
• Application Number:
  US11/064,242
• Publication Number:
  US 20050166092A1
• Time in Patent Office: 1,218 Days
• Field of Search: 714/28, 714/33, 714/34, 714/35, 714/38, 717/127, 717/128
• US Class Current: 714/28
• CPC Class Codes: G06F 11/3656 using a specific debug interface

Abstract

In-circuit-emulation of an integrated circuit includes a digital data processor capable of executing program instructions. A first debug event is detected during normal program execution. The causes the in-circuit-emulation to suspend program execution except for real time interrupts. A debug frame counter increments on each interrupt and decrements on each return from interrupt. If a debug event is detected during an interrupt service routine, that interrupt service routine is suspended and the count of the debug frame counter is stored. Execution of other interrupt service routines in response to corresponding interrupts is still permitted. The integrated circuit includes plural debug event detectors and the debug frame count is stored at the detector detecting a debug event during an interrupt service routine. This permits a determination of the order of interrupts triggering debug events by reading the stored debug frame count from each debug event detector.

Claims

1. A method of in circuit emulation of an integrated circuit including a digital data processor capable of executing program instructions, comprising the steps of:

detecting a first debug event during normal program execution;

upon detection of the first debug event suspending normal program execution while permitting at least one type interrupt service routine executed in response to a corresponding interrupt;

incrementing a debug frame counter upon each of the at least one type interrupt received while suspending normal program execution;

decrementing the debug frame counter upon each return from interrupt received while suspending normal program execution;

detecting at least one second debug event during an interrupt service routine executing while suspending normal program execution;

upon detection of the second debug event suspending program execution of the interrupt service routine while permitting execution of other interrupt service routines in response to corresponding interrupts; and

storing the count of said debug frame counter upon each second debug event.

2. The method of claim 1, wherein said integrated circuit includes a plurality of debug event detectors, and wherein:

said step of detecting a first debug event occurs at a first one of the plurality of debug event detectors;

said step of detecting a second debug event occurs at a second one of the plurality of debug event detectors; and

said step of storing the count of said debug frame counter occurs at said second one of the plurality of debug event detectors.

3. The method of claim 2, further comprising:

determining an order of interrupts triggering second debug events by reading said stored count of said debug frame counter from each of said debug event detectors.

4. The method of claim 2, wherein said integrated circuit includes a plurality of emulation peripherals, each emulation peripheral including a plurality of debug event detectors and further comprising:

limiting each of said emulation peripherals to triggering a single debug event before being cleared.

5. The method of claim 4, wherein:

said limiting step includes

upon detecting a debug event at each debug event detector checking the stored count of the debug frame counter, and

prohibiting triggering a debug event if the stored count of the debug frame counter is nonzero.

6. The method of claim 1, further comprising:

resetting the debug frame counter upon return to normal program execution.

7. The method of claim 1, further comprising:

resetting the debug frame counter upon an abort interrupt corresponding to an unrecoverable error during an interrupt service routine.