Method and apparatus of compensating for signal receiving error at receiver in packet-based communication system

• US 7,392,450 B2
• Filed: 07/08/2004
• Issued: 06/24/2008
• Est. Priority Date: 07/08/2004
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Lin, Jeff
• Primary Examiner(s): Britt; Cynthia
• Assistant Examiner(s): Merant; Guerrier
• Application Number:
  US10/885,649
• Publication Number:
  US 20060010361A1
• Time in Patent Office: 1,447 Days
• Field of Search: 714/747, 714/746, 714/700
• US Class Current: 714/747
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data
• CPC Class Codes: H04L 1/0075 Transmission of coding parameters to receiver H04L1/0023 takes precedence
• CPC Class Codes: H04L 2027/003 at baseband only
• CPC Class Codes: H04L 2027/0089 In-band signals
• CPC Class Codes: H04L 25/0236 using estimation of the other symbols
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296
• CPC Class Codes: H04L 27/2657 Carrier synchronisation

Abstract

A method and an apparatus of compensating for a signal receiving error at a receiver in a packet-based communication system. In the invention, frequency offset estimation and DC offset estimation obtained in a current packet are re-used in a next packet if the receiver is an intended recipient of the current packet and the current packet is received correctly, verified by CRC-32 checking in the PHY layer and the DA checking in the MAC layer, respectively. Thereby, the overall receiver performance and stability can be improved from packet to packet and the estimation algorithm is simplified.

Claims

1. A method for processing a received signal in a PHY (Physical) layer of a receiver in a packet-based communication system, comprising the steps of:

compensating the received signal for a signal receiving error in a current packet with an estimated data obtained by re-using a previously latched estimated data to generate a portion of a compensated signal when a number of successive times of estimation failures in previous packets is smaller than a predetermined number;

compensating the received signal for the signal receiving error in the current packet with an estimated data obtained by using a training sequence in the current packet to generate the portion of the compensated signal when the number of successive times of the estimation failures in the previous packets is greater than the predetermined number;

decoding the compensated signal as a decoded signal and delivering the decoded signal to a MAC (Medium Access Control) layer of the receiver;

receiving from the MAC layer a signal for indicating whether or not the receiver is an intended recipient of the current packet;

determining whether or not the current packet is received correctly;

incrementing the number of successive times of estimation failures by one if the receiver is an intended recipient of the current packet and the current packet is not received correctly; and

latching the estimated data used in the current packet if the receiver is an intended recipient of the current packet and the current packet is received correctly.

2. The method of claim 1, wherein said estimated data is DC offset estimation.

3. The method of claim 1, wherein said estimated data is frequency offset estimation, and the signal receiving error is a frequency offset error.

4. The method of claim 1, wherein said estimated data is channel estimation, and the signal receiving error is a channel distortion.

5. The method of claim 1, wherein whether or not the receiver is an intended recipient of the current packet is determined by verifying whether or not a destination address of the current packet matches an identity address of the receiver.

6. The method of claim 1, wherein whether or not the current packet is received correctly is determined by cyclic redundancy check (CRC).

7. The method of claim 1, further comprising:

continuing to improve accuracy of the estimated data used in the current packet until the end of the current packet.

8. A receiver for a packet-based communication system, comprising:

a compensation circuit, compensating The a received signal for a signal receiving error in a current packet with an estimated data obtained by re-using a previously latched estimated data to obtain a portion of a compensated signal when a re-use control signal is asserted, and compensating the received signal for the signal receiving error in the current packet with an estimated data obtained by using a training sequence in the current packet to obtain the portion of the compensated signal when the re-use control signal is not asserted;

an estimation circuit for generating the estimated data in a current packet;

a decoding circuit for decoding the compensated signal;

a circuit for verifying whether or not the receiver is an intended recipient of the current packet;

a circuit for verifying whether or not the current packet is received correctly;

a circuit for incrementing a number of successive times of estimation failures by one if the receiver is an intended recipient of the current packet and the current packet is not received correctly;

a buffer circuit for latching the estimated data used in the current packet if the receiver is an intended recipient of the current packet and the current packet is received correctly; and

a re-use control circuit , asserting the re-use control signal when the number of successive times of the estimation failures in previous packets is smaller than a predetermined number, and de-asserting the re-use control signal when the number of successive times of the estimation failures in the previous packets is greater than the predetermined number.

9. The receiver for a packet-based communication system of claim 8, wherein said estimated data is DC offset estimation.

10. The receiver for a packet-based communication system of claim 8, wherein said estimated data is frequency offset estimation, and the signal receiving error is a frequency offset error.

11. The receiver for a packet-based communication system of claim 8, wherein said estimated data is channel estimation, and the signal receiving error is a channel distortion.

12. The receiver for a packet-based communication system of claim 8, wherein the circuit for verifying whether or not the receiver is an intended recipient of the current packet verifies whether or not a destination address of the current packet matches an identity address of the receiver.

13. The receiver for a packet-based communication system of claim 8, wherein the circuit for verifying whether or not the current packet is received correctly is a cyclic redundancy check (CRC) circuit.

14. The receiver for a packet-based communication system of claim 8, wherein the estimation circuit further improves accuracy of the estimated data used in the current packet until the end of the current packet.