Method for reducing within chip device parameter variations

• US 7,393,703 B2
• Filed: 05/10/2006
• Issued: 07/01/2008
• Est. Priority Date: 05/10/2006
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward Joseph, Anderson, Brent Alan, Gabor, Allen H., Rankin, Jed Hickory, Butt, Shahid Ahmad, Lindo, Patrick Edward
• Primary Examiner(s): Thai; Luan
• Application Number:
  US11/382,489
• Publication Number:
  US 20070264729A1
• Time in Patent Office: 783 Days
• Field of Search: 438/11, 438/14
• US Class Current: 438/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.

Claims

1. A method, comprising:

on a first wafer having a first arrangement of integrated circuit chips, each integrated circuit chip divided into a second arrangement of regions, measuring a same test device parameter of test devices distributed in different regions of said second arrangement of regions, one or more same regions of all integrated circuit chips of said first wafer including identically designed field effect transistors; and

on a second wafer having said first arrangement of integrated circuit chips, each integrated circuit chip divided into said second arrangement of regions, adjusting a same functional device parameter of identically designed field effect transistors within one or more same regions of all integrated circuit chips of said second wafer based on values of said same test device parameter measured on test devices in regions of said integrated circuit chip of said first wafer corresponding to said one or more same regions of said integrated circuit chips of said second wafer by a non-uniform adjustment of physical polysilicon gate widths of said identically designed field effect transistors from region to region within each integrated circuit chip.

2. The method of claim 1, wherein said test devices are selected from the group consisting of ring oscillators, field effect transistors and polysilicon resistors.

3. The method of claim 1, wherein said same test device parameter is selected from the group consisting of switching frequency, threshold voltage, source-to-drain resistance, gate capacitance, drain current, gate voltage, effective channel length and sheet resistance.

4. The method of claim 1, wherein said functional device parameter is selected from the group consisting of threshold voltage, source-to-drain resistance and gate polysilicon sheet resistance.

5. The method of claim 1, further including:

at a photolithographic fabrication step defining said physical polysilicon gate lengths of said identically designed field effect transistors, adjusting an actinic radiation exposure dose and exposing a photoresist layer formed on said second wafer for each region of each integrated circuit chip of said second wafer to said adjusted dose of actinic radiation.

6. The method of claim 5, wherein said adjusting said actinic radiation dose includes selectively opening and closing trim tabs of an exposure slit of a photolithographic exposure tool as said exposure slit is scanned over different regions of each of said integrated circuit chips.

7. The method of claim 6, wherein said adjusting said actinic radiation dose further includes adjusting actinic radiation intensity, actinic radiation pulse width, actinic radiation pulse frequency, slit width, slit scan speed or combinations thereof as said exposure slit is scanned over different regions of each of said integrated circuit chips.

8. The method of claim 5, wherein said adjusting said actinic radiation dose includes adjusting actinic radiation intensity, actinic radiation pulse width, actinic radiation pulse frequency, slit width, slit scan speed or combinations thereof as an exposure slit of a photolithographic exposure tool is scanned over different regions of each of said integrated circuit chips.

9. The method of claim 1, further including:

at a fabrication step defining said physical polysilicon gate lengths of said identically designed field effect transistors, exposing a photoresist layer formed on said second wafer to actinic radiation through a patterned photomask having a chip region divided into said second arrangement of regions, a width of pattern features defining said polysilicon physical gate lengths in at least two of said regions of said chip region being different.

10. The method of claim 1, further including:

at a fabrication step defining said physical polysilicon gate lengths, exposing a photoresist layer formed on said second wafer to a first dose of actinic radiation through a first patterned photomask having a first chip region divided into said second arrangement of multiple regions, a width of pattern features defining polysilicon physical gate lengths of said identically designed field effect transistors being the same on all regions of said first chip region; and

exposing said photoresist layer to a second dose of actinic radiation through a second patterned photomask having a second chip region divided into said second arrangement of multiple regions, at least two of said regions of said second chip region attenuating said second dose of actinic radiation differently.

11. The method of claim 1, further including:

performing a source/drain ion implantation of said identically designed field effect transistors of said first and second wafers; and

after performing said source/drain ion implantation, performing a rapid thermal anneal of said first and second wafers.

12. A method, comprising:

on a first wafer having a first arrangement of integrated circuit chips, each integrated circuit chip divided into a second arrangement of regions, measuring a same test device parameter of test devices distributed in different regions of said second arrangement of regions, one or more same regions of all integrated circuit chips of said first wafer including identically designed field effect transistors; and

on a second wafer having said first arrangement of integrated circuit chips, each integrated circuit chip divided into said second arrangement of regions, adjusting a same functional device parameter of identically designed field effect transistors within one or more same regions of all integrated circuit chips of said second wafer based on values of said same test device parameter measured on test devices in regions of said integrated circuit chip of said first wafer corresponding to said one or more same regions of said integrated circuit chips of said second wafer by a non-uniform adjustment of physical source/drain ion implantation fabrication steps of said identically designed field effect transistors from region to region within each integrated circuit chip.

13. The method of claim 12, wherein said test devices are selected from the group consisting of ring oscillators, field effect transistors and polysilicon resistors.

14. The method of claim 12, wherein said same test device parameter is selected from the group consisting of switching frequency, threshold voltage, source-to-drain resistance, gate capacitance, drain current, gate voltage, effective channel length and sheet resistance.

15. The method of claim 12, wherein said functional device parameter is selected from the group consisting of threshold voltage, source-to-drain resistance and gate polysilicon sheet resistance.

16. The method of claim 12, further including:

performing a same source/drain ion implantation of said identically designed field effect transistor in all regions of all said integrated circuit chips of said first and second wafers; and

performing a source/drain trim ion-implantation of said identically designed field effect transistors in each integrated circuit chip of said second wafer, either (i) an ion implantation dose, (ii) an ion implantation energy, or (iii) both said ion implantation dose and energy being different in at least two regions of each integrated circuit chip.

17. The method of claim 16, further including:

performing a same source/drain extension ion implantation of said identically designed field effect transistor in all regions of all said integrated circuit chips of said first and second wafers.

18. The method of claim 17, further including:

performing a same halo well ion implantation of said identically designed field effect transistor in all regions of all said integrated circuit chips of said first and second wafers.

19. The method of claim 12, further including:

performing a same source/drain ion implantation of said identically designed field effect transistor in all regions of each integrated circuit chip; and

performing a source/drain trim ion-implantation of each integrated circuit chip of said second wafer, said identically designed field effect transistors in at least one region of each integrated circuit chip receiving said source/drain trim ion implantation and corresponding said identically designed field effect transistors in at least one other region of each integrated circuit chip not receiving said source/drain trim ion implantation.

20. The method of claim 19, further including:

performing a same source/drain extension ion implantation of said identically designed field effect transistor in all regions of all said integrated circuit chips.

21. The method of claim 20, further including:

performing a same halo well ion implantation of said identically designed field effect transistor in all regions of all said integrated circuit chips.

22. The method of claim 12, further including:

performing a source/drain ion implantation of said identically designed field effect transistors of said first and second wafers; and

after performing said source/drain ion implantation, performing a rapid thermal anneal of said first and second wafers.