Unmolded package for a semiconductor device

• US 7,393,718 B2
• Filed: 08/11/2005
• Issued: 07/01/2008
• Est. Priority Date: 02/01/2001
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Joshi, Rajeev
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US11/202,510
• Publication Number:
  US 20050280161A1
• Time in Patent Office: 1,055 Days
• Field of Search: 257/686, 257/737, 257/738, 257/777, 257/778, 438/107, 438/108
• US Class Current: 438/107
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/145 Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/074 Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15321 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H05K 3/3436 having an array of bottom contacts, e.g. pad grid array or ball grid array components

Abstract

A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the serves as the drain connections while the solder balls serve as the source and gate connections.

Claims

1. A method comprising:

obtaining a substrate comprising a first side and a second side;

attaching a semiconductor die comprising a periphery to the first side of the substrate, the semiconductor die comprising a first surface comprising a drain, and a second surface opposite the first surface, wherein the second surface comprises source and gate regions;

attaching conductive structures to the substrate outside of the periphery of the semiconductor die, wherein the conductive structures are substantially coplanar with the semiconductor die; and

attaching the substrate to a printed circuit board using the conductive structures, wherein there is no underfill material between the substrate and the printed circuit board,

wherein after attaching the substrate to the printed circuit board, the source and gate regions of the semiconductor die at the second surface are electrically coupled to the substrate, and wherein the conductive structures provide communication between source and gate regions at the second surface of the semiconductor die and the printed circuit board, and wherein the drain at the first surface of the semiconductor die is electrically coupled to the printed circuit board.

2. The method of claim 1 wherein the conductive structures comprise solder.

3. The method claim 1 wherein the substrate is an insulated metal substrate.

4. The method of claim 1 further comprising attaching a second die on the second side of the substrate.

5. The method of claim 1 wherein the substrate comprises a metallized ceramic.

6. The method of claim 1 wherein the substrate is rigid.

7. The method of claim 1 wherein the substrate comprises an epoxy material.

8. The method of claim 1 further comprising flipping the substrate with the attached semiconductor die prior to attaching the substrate to the circuit board.

9. A method comprising:

obtaining a substrate comprising a first side and a second side;

attaching a semiconductor die comprising a periphery to the first side of the substrate, the semiconductor die comprising a first surface comprising an output region, and a second surface opposite the first surface, wherein the second surface comprises an input region;

attaching conductive structures to the substrate outside of the periphery of the semiconductor die, wherein the conductive structures are substantially coplanar with the semiconductor die; and

attaching the substrate to a printed circuit board using the conductive structures, wherein there is no underfill material between the substrate and the printed circuit board,

wherein after attaching the substrate to the printed circuit board, the output region at the first surface of the die is electrically coupled to the circuit board, and wherein the conductive structures provide communication between the input region at the second surface of the semiconductor die and the printed circuit board.

10. The semiconductor device of claim 9 wherein the conductive structures comprise solder.

11. The semiconductor device of claim 9 wherein the substrate is an insulated metal substrate.

12. The method of claim 9 wherein the substrate is rigid.

13. The method of claim 9 further comprising flipping the substrate with the attached semiconductor die prior to attaching the substrate to the circuit board.