Atomic layer deposition of Zrx Hfy Sn1-x-y O2 films as high k gate dielectrics

• US 7,393,736 B2
• Filed: 08/29/2005
• Issued: 07/01/2008
• Est. Priority Date: 08/29/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): Nhu; David
• Application Number:
  US11/215,530
• Publication Number:
  US 20070049051A1
• Time in Patent Office: 1,037 Days
• Field of Search: 438/197, 438/199, 438/660, 438/602, 438/603, 438/604, 438/680, 438/681, 438/723, 438/724, 438/743, 438/744, 438/756, 438/757, 438/753, 438/778, 438/381
• US Class Current: 438/197
• CPC Class Codes: C23C 16/40 Oxides
• CPC Class Codes: C23C 16/45529 specially adapted for making a layer stack of alternating different compositions or gradient compositions
• CPC Class Codes: C23C 16/45531 specially adapted for making ternary or higher compositions
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02194 the material containing more than one metal element
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/3142 of nano-laminates, e.g. alternating layers of Al203-Hf02
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO₂), hafnium oxide (HfO₂) and tin oxide (SnO₂) acting as a single dielectric layer with a formula of Zr_XHf_YSn_1-X-YO₂, and a method of fabricating such a dielectric layer is described that produces a reliable structure with a high dielectric constant (high k). The dielectric structure is formed by depositing zirconium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing hafnium oxide onto the substrate using precursor chemicals, followed by depositing tin oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric may be used as a gate insulator, a capacitor dielectric, or as a tunnel insulator in non-volatile memories, because the high dielectric constant (high k) provides the functionality of a much thinner silicon dioxide film.

Claims

1. A method comprising:

forming a substantially planar nanolaminate dielectric layer including at least zirconium oxide, hafnium oxide and tin oxide on a surface of a substrate by atomic layer deposition; and

forming a metal layer on the planar nanolaminate dielectric layer.

2. The method of claim 1, wherein forming the zirconium oxide includes forming an amorphous oxide having a formula ZrO₂.

3. The method of claim 1, wherein forming the hafnium oxide includes forming an amorphous oxide having a formula of HfO₂.

4. The method of claim 1, wherein forming the tin oxide includes forming an amorphous oxide having a formula of SnO₂.

12. The method of claim 1, wherein the substrate includes a conductive layer disposed below the planar nanolaminate dielectric layer.

13. The method of claim 12, wherein the method is a method of forming a capacitive device.

25. The method of claim 1, wherein the dielectric film has a composition that remains substantially amorphous after exposure to temperatures of up to 900°

C.

26. The method of claim 1, wherein the planar nanolaminate dielectric film is formed of alternating layers of zirconium oxide, hafnium oxide and tin oxide.

5. A method comprising:

forming a substantially planar nanolaminate dielectric layer including at least zirconium oxide, hafnium oxide and tin oxide on a surface of a substrate by atomic layer deposition; and

forming a metal layer on the nanolaminate dielectric layer

wherein the zirconium oxide, the hafnium oxide, and the tin oxide are miscible and form a single alloyed layer having a general formula of Zr_XHf_YSn_ZO₂.

6. The method of claim 5, wherein X has a range of from 0.70 to 0.85, Y has a range of from 0.05 to 0.25, and Z=1−

X−

Y.

7. The method of claim 5, wherein X is 0.81, Y is 0.12, and Z is 0.07.

8. The method of claim 5, wherein the substrate includes at least two diffused regions having a first conductivity type, separated by a region of a second conductivity type disposed below the planar nanolaminate dielectric layer and metal layer.

9. The method of claim 8, wherein the substrate is a silicon crystal having a <

100>

crystal orientation at the surface and the planar nanolaminate dielectric layer has an EOT of less than 1.0 nm.

10. The method of claim 9, wherein the method is a method of forming a transistor device.

11. The method of claim 9, wherein the method is a method of forming a memory device.

14. The method of claim 5, wherein the planar nanolaminate dielectric layer has a root mean square surface roughness that is less than two percent of the layer thickness.

15. A method comprising:

forming a substantially planar nanolaminate dielectric layer including at least zirconium oxide, hafnium oxide and tin oxide on a surface of a substrate by atomic layer deposition; and

forming a metal layer on the planar nanolaminate dielectric layer;

wherein the zirconium oxide layer is formed with a first precursor selected from the list including tetrakis diethyl amino zirconium, zirconium tetrachloride, zirconium tetraiodide, zirconium tertiary-butyloxide and zirconium nitride.

16. The method of claim 15, wherein the hafnium oxide layer is formed with a first precursor selected from the list including hafnium tetra chloride, hafnium tetraiodide, hafnium tertiary-butyloxide and hafnium nitride.

17. The method of claim 16, wherein the tin oxide layer is formed with a first precursor selected from the list including tin tetrachloride, tin tetraiodide and organo-metallic tin.

18. The method of claim 17, wherein the zirconium oxide, hafnium oxide and tin oxide are each one of three components of the planar nanolaminate dielectric layer that form a single alloyed planar nanolaminate dielectric layer having a dielectric constant of greater than 17.

19. The method of claim 18, wherein the planar nanolaminate dielectric layer is separated from the substrate by a diffusion barrier.

20. The method of claim 18, wherein each of the three components of the dielectric layer is formed at a temperature of less than 300°

C.

21. The method of claim 18, wherein each of the three components of the dielectric film has a second precursor that follows the first precursor at a selected later time selected from a list including water vapor, hydrogen peroxide, oxygen, oxygen plasma, ozone, nitrogen oxides, sequential combinations thereof, and simultaneous combinations thereof.

22. The method of claim 18, wherein each of the three components of the dielectric film has at least one purge gas cycle included in the forming process selected from a list including nitrogen, hydrogen, argon, neon, krypton, and combinations thereof.

23. The method of claim 22, wherein at least one of the three metal oxide films is formed at a reduced pressure.

24. The method of claim 23, wherein the reduced pressure is around 10⁻

6 Torr.

27. A method comprising:

forming a substantially planar nanolaminate dielectric layer including a plurality of alternating layers of at least zirconium oxide, hafnium oxide and tin oxide on a surface of a substrate by atomic layer deposition; and

forming a metal layer on the planar nanolaminate dielectric layer;

wherein each of the alternating layers is formed of a selected number of atomic layer deposition cycles to obtain a desired ratio of zirconium to hafnium, and of zirconium to tin in the planar nanolaminate dielectric layer.

28. The method of claim 27, wherein the zirconium oxide layer is formed of a selected number of individual layers of zirconium oxide, each individual layer formed by a single cycle of the atomic layer deposition process having a thickness of about 0.50 nm.

29. The method of claim 27, wherein the hafnium oxide layer is formed of a selected number of individual layers of hafnium oxide, each individual layer formed by a single cycle of the atomic layer deposition process having a thickness of about 0.033 nm.

30. The method of claim 27, wherein the tin oxide layer is formed of a selected number of individual layers of tin oxide, each individual layer formed by a single cycle of the atomic layer deposition process having a thickness of about 0.013 nm.

31. A method comprising:

forming a substantially planar nanolaminate dielectric layer including at least zirconium oxide, hafnium oxide and tin oxide on a surface of a substrate by atomic layer deposition; and

forming a metal layer on the planar nanolaminate dielectric layer;

wherein the planar nanolaminate dielectric layer is formed by;

forming a first portion of the planar nanolaminate dielectric layer, including exposing an activated substrate surface at a preselected temperature to a first precursor material for a preselected first time period and a preselected flow volume of the first precursor material to saturate the substrate surface with the first precursor material;

exposing the substrate surface to a preselected volume of a first purge material for a preselected second time period to remove substantially all of a non-absorbed portion of the first precursor material from the substrate surface;

exposing the substrate surface to a preselected volume of a first reactant material for a preselected third time period to react with the absorbed portion of the first precursor material on the substrate surface to form a first dielectric material having a first thickness;

exposing the substrate surface to a preselected volume of a second purge material for a preselected fourth time period to remove substantially all of a non-reacted portion of the first reactant material, and a first plurality of gaseous reaction byproducts from the substrate surface;

repeating the first portion forming until a first portion thickness reaches a predetermined first final value;

forming a second portion of the planar nanolaminate dielectric layer, including exposing the substrate surface to a second precursor material for a preselected fifth time period and a preselected flow volume of the second precursor material to saturate the substrate surface with the second precursor material;

exposing the substrate surface to a preselected volume of a third purge material for a preselected sixth time period to remove substantially all of a non-absorbed portion of the second precursor material from the substrate surface;

exposing the substrate surface to a preselected volume of a second reactant material for a preselected seventh time period to react with the absorbed portion of the second precursor material on the substrate surface to form a second dielectric material having a second thickness;

exposing the substrate surface to a preselected volume of a fourth purge material for a preselected eighth time period to remove substantially all of a non-reacted portion of the second reactant material, and a second plurality of gaseous reaction byproducts from the substrate surface;

repeating the second portion forming until a second portion thickness reaches a predetermined second final value;

forming a third portion of the planar nanolaminate dielectric layer, including exposing the substrate surface to a third precursor material for a preselected ninth time period and a preselected flow volume of the third precursor material to saturate the substrate surface with the third precursor material;

exposing the substrate surface to a preselected volume of a fifth purge material for a preselected tenth time period to remove substantially all of a non-absorbed portion of the third precursor material from the substrate surface;

exposing the substrate surface to a preselected volume of a third reactant material for a preselected eleventh time period to react with the absorbed portion of the third precursor material on the substrate surface to form a third dielectric material having a third thickness;

exposing the substrate surface to a preselected volume of a sixth purge material for a preselected twelfth time period to remove substantially all of a non-reacted portion of the third reactant material, and a third plurality of gaseous reaction byproducts from the substrate surface;

repeating the third portion forming until a third portion thickness reaches a predetermined value; and

repeating the first, second and third forming until a preselected final planar nanolaminate dielectric layer thickness is obtained.

32. The method of claim 31, wherein the first, second and third portions are formed of miscible materials and form a single alloyed dielectric layer after heat cycling.

33. The method of claim 32, wherein the thickness of the first, second and third portions of the planar nanolaminate dielectric layer each have a thickness that is low enough to closely intermingle the portions to form an effectively single layer film having physical properties determined by the ratios of the first, second and third portions of the planar nanolaminate dielectric layer.

34. The method of claim 32, wherein the first, second and third portions are formed of materials having approximate formulas of ZrO₂, HfO₂ and SnO₂.

35. A method comprising:

forming an integrated circuit including at least one substantially planar nanolaminate dielectric layer containing at least zirconium oxide, hafnium oxide and tin oxide by atomic layer deposition; and

forming a conductive layer on the planar nanolaminate dielectric layer.

36. The method of claim 35, wherein the conductive layer comprises a metal.

37. The method of claim 36, wherein the method includes forming the planar nanolaminate dielectric layer as a gate insulator having a portion of the metal layer as a gate of a transistor in the integrated circuit.

38. The method of claim 35, wherein the method includes forming the planar nanolaminate dielectric layer as a gate insulator in a CMOS transistor in the integrated circuit.

39. The method of claim 37, wherein the method includes forming the metal layer as an electrode of a capacitor and forming the planar nanolaminate dielectric layer as a dielectric of the capacitor.

40. The method of claim 35, wherein the planar nanolaminate dielectric layer has a general formula of Zr_XHf_YSn_ZO₂.

41. The method of claim 40, wherein X has a range of from 0.70 to 0.85, Y has a range of from 0.05 to 0.25, and Z=1−

X−

Y.

42. The method of claim 40, wherein X is 0.81, Y is 0.12, and Z is 0.07.

43. A method, comprising:

forming a memory array in a substrate including;

forming at least one atomic layer deposition planar nanolaminate dielectric layer containing at least zirconium oxide, hafnium oxide and tin oxide in an integrated circuit wherein the planar nanolaminate dielectric layer is in contact with substantially all of a top surface of a substrate containing the integrated circuit;

depositing a conductive layer contacting the planar nanolaminate dielectric layer; and

forming an address decoder in the substrate, the address decoder coupled to the memory array.

44. The method of claim 43, wherein the method is a method of forming a flash memory device, and forming the dielectric layer includes forming the dielectric layer as an inter-gate insulator having the conductive layer as a gate of a transistor in the flash memory device.

45. The method of claim 43, wherein the method is a method of forming a memory device, including forming the conductive layer as an electrode of a capacitor and forming the planar nanolaminate dielectric layer as a dielectric of the capacitor in the memory device.

46. The method of claim 43, wherein the planar nanolaminate dielectric layer has a general formula of Zr_XHf_YSn_ZO₂.

47. The method of claim 46, wherein X has a range of from 0.70 to 0.85, Y has a range of from 0.05 to 0.25, and Z=1−

X−

Y.

48. The method of claim 46, wherein X is 0.81, Y is 0.12, and Z is 0.07.

49. A method comprising:

providing a controller;

coupling an integrated circuit to the controller, wherein the integrated circuit includes a substantially planar nanolaminate dielectric layer contacting a conductive layer, the dielectric comprising zirconium oxide, hafnium oxide and tin oxide, wherein forming the planar nanolaminate dielectric layer contacting the conductive layer includes;

forming the planar nanolaminate dielectric layer by atomic layer deposition; and

depositing the conductive layer such that the conductive layer contacts the planar nanolaminate dielectric layer.

50. The method of claim 49, wherein coupling an integrated circuit to the controller includes coupling a memory device formed as the integrated circuit.

51. The method of claim 49, wherein providing a controller includes providing a processor.

52. The method of claim 49, wherein coupling an integrated circuit to the controller includes coupling a mixed signal integrated circuit formed as the integrated circuit having the planar nanolaminate dielectric layer contacting the conductive layer.

53. The method of claim 49, wherein the method is a method of forming an information handling system.

54. The method of claim 49, wherein the planar nanolaminate dielectric layer has a general formula of Zr_XHf_YSn_ZO₂.

55. The method of claim 54, wherein X has a range of from 0.70 to 0.85, Y has a range of from 0.05 to 0.25, and Z=1−

X−

Y.

56. The method of claim 54, wherein X is _0.81, Y is 0.12, and Z is 0.07.

57. A method comprising:

forming a planar nanolaminate dielectric layer including at least zirconium oxide, hafnium oxide and tin oxide on a surface of a substrate by atomic layer deposition; and

forming a metal layer on the planar nanolaminate dielectric layer;

wherein the zirconium oxide, the hafnium oxide, and the tin oxide are miscible and form a single alloyed layer having a general formula of Zr_XHf_YSn_ZO₂.

58. A method comprising:

forming a planar nanolaminate dielectric layer including at least zirconium oxide, hafnium oxide and tin oxide on a surface of a substrate by atomic layer deposition; and

forming a metal layer on the planar nanolaminate dielectric layer;

wherein the substrate includes at least two diffused regions having a first conductivity type, separated by a region of a second conductivity type disposed below the planar nanolaminate dielectric layer and metal layer.

59. A method comprising:

forming a planar nanolaminate dielectric layer including at least zirconium oxide, hafnium oxide and tin oxide on a surface of a substrate by atomic layer deposition; and

forming a metal layer on the planar nanolaminate dielectric layer;

wherein the planar nanolaminate dielectric layer has a root mean square surface roughness that is less than two percent of the layer thickness.