Charge balance field effect transistor

• US 7,393,749 B2
• Filed: 06/08/2006
• Issued: 07/01/2008
• Est. Priority Date: 06/10/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Challa, Ashok, Yilmaz, Hamza, Calafut, Daniel, Kraft, Nathan, Sapp, Steven
• Primary Examiner(s): Pham; Thanh V
• Application Number:
  US11/450,903
• Publication Number:
  US 20060281249A1
• Time in Patent Office: 754 Days
• Field of Search: 438/259, 438/270, 257/330, 257/332
• US Class Current: 438/259
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A field effect transistor is formed as follows. A semiconductor region of a first conductivity type with an epitaxial layer of a second conductivity extending over the semiconductor region is provided. A trench extending through the epitaxial layer and terminating in the semiconductor region is formed. A two-pass angled implant of dopants of the first conductivity type is carried out to thereby form a region of first conductivity type along the trench sidewalls. A threshold voltage adjust implant of dopants of the second conductivity type is carried out to thereby convert a conductivity type of a portion of the region of first conductivity type extending along upper sidewalls of the trench to the second conductivity type. Source regions of the first conductivity type flanking each side of the trench are formed.

Claims

1. A method of forming a FET, comprising:

providing a semiconductor region of a first conductivity type with an epitaxial layer of a second conductivity extending over the semiconductor region;

forming a trench extending through the epitaxial layer and terminating in the semiconductor region;

performing a two-pass angled implant of dopants of the first conductivity type to thereby form a region of first conductivity type along the trench sidewalls;

performing a threshold voltage adjust implant of dopants of the second conductivity type to thereby convert a conductivity type of a portion of the region of first conductivity type extending along upper sidewalls of the trench to the second conductivity type; and

forming source regions of the first conductivity type flanking each side of the trench.

2. The method of claim 1 further comprising:

forming a shield electrode in a lower portion of the trench such that an upper portion of the shield electrode extends in the epitaxial layer and a lower portion of the shield electrode extends in the semiconductor region, the shield electrode being insulated from the epitaxial layer and the semiconductor region by a shield dielectric;

forming a gate dielectric layer along upper sidewalls of the trench; and

forming a gate electrode in the trench over but insulated from the shield electrode.

3. The method of claim 1 further comprising:

forming heavy body regions of the second conductivity type in the epitaxial layer;

forming a dielectric cap extending over the trench and a portion of each source region; and

forming a source interconnect layer contacting the source regions and the heavy body regions.

4. The method of claim 1 further comprising:

prior to the step of performing a two pass angled implant, performing a two pass angled implant of dopants of the second conductivity type to thereby form a region of second conductivity type along trench sidewalls,

wherein the region of second conductivity type laterally extends further than the region of first conductivity type, and

wherein a doping concentration of the two pass angled implant of dopants of the first conductivity type and the two pass angled implant of dopants of the second conductivity type are selected so that substantial charge balance is obtained between the region of first conductivity type and the region of second conductivity type.

5. The method of claim 1 wherein the first conductivity type is n-type and the second conductivity type is p-type.

6. The method of claim 1 wherein the semiconductor region is a highly doped substrate.

7. A method of forming a MOSFET comprising:

providing a substrate of a first conductivity type;

forming an epitaxial layer of a second conductivity over the substrate;

forming a trench extending through the epitaxial layer and terminating in the substrate;

performing a two-pass angled implant of dopants of the first conductivity type to thereby form a region of first conductivity type along the trench sidewalls;

forming a shield electrode in a lower portion of the trench such that an upper portion of the shield electrode extends in the epitaxial layer and a lower portion of the shield electrode extends in the substrate, the shield electrode being insulated from the epitaxial layer and the substrate by a shield dielectric;

forming a gate dielectric layer along upper sidewalls of the trench;

forming a gate electrode in the trench over but insulated from the shield electrode;

performing a threshold voltage adjust implant of dopants of the second conductivity type to thereby convert the conductivity type of a portion of the region of the first conductivity type extending along upper sidewalls of the trench to the second conductivity type; and

forming source regions of the first conductivity type flanking each side of the trench.

8. The method of claim 7 further comprising:

forming heavy body regions of the second conductivity type in the epitaxial layer;

forming a dielectric cap extending over the trench and a portion of each source region; and

forming a source interconnect layer contacting the source regions and the heavy body regions.

9. The method of claim 7 further comprising:

prior to the step of performing a two pass angled implant, performing a two pass angled implant of dopants of the second conductivity type to thereby form a region of second conductivity type along trench sidewalls,

wherein the region of second conductivity type laterally extends further than the region of first conductivity type, and

wherein a doping concentration of the two pass angled implant of dopants of the first conductivity type and the two pass angled implant of dopants of the second conductivity type are selected so that substantial charge balance is obtained between the region of first conductivity type and the region of second conductivity type.

10. The method of claim 7 wherein the first conductivity type is n-type and the second conductivity type is p-type.

11. A MOSFET comprising:

a trench extending into a semiconductor region;

a shield electrode in a lower portion of the trench, the shield electrode being insulated from the semiconductor region by a shield dielectric;

a gate electrode in an upper portion of the trench, the gate electrode being over but insulated from the shield electrode;

wherein the semiconductor region comprises;

a substrate of a first conductivity type;

a first silicon region of a second conductivity type over the substrate, the first silicon region having a first portion extending to a depth intermediate a top surface and a bottom surface of the gate electrode, the first silicon region having a second portion extending to a depth intermediate a top surface and a bottom surface of the shield electrode;

a second silicon region of the first conductivity type between the trench and the second portion of the first silicon region, the second silicon region having a laterally-graded doping concentration decreasing in a direction away from the trench sidewalls; and

a source region of the first conductivity type in the first silicon region, the source region being adjacent the trench.

12. The MOSFET of claim 11 wherein the trench terminates within the substrate.

13. The MOSFET of claim 11 wherein the first portion of the first silicon region includes a vertically-extending channel region defined by a spacing between the source region and the second silicon region.

14. The MOSFET of claim 11 further comprising:

a heaving body region of the second conductivity type in the first silicon region; and

a source interconnect layer electrically contacting the source region and the heavy body region but being insulated from the gate electrode.