Low temperature CVD process with selected stress of the CVD layer on CMOS devices

• US 7,393,765 B2
• Filed: 04/19/2007
• Issued: 07/01/2008
• Est. Priority Date: 06/05/2002
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Ramaswamy, Kartik, Hanawa, Hiroji, Collins, Kenneth S., Nguyen, Andrew, Al-Bayati, Amir, Gallo, Biagio
• Primary Examiner(s): Ghyka; Alexander G
• Application Number:
  US11/788,523
• Publication Number:
  US 20070212811A1
• Time in Patent Office: 439 Days
• Field of Search: 438/199, 438/513, 438/515, 438/680, 438/780
• US Class Current: 438/515
• CPC Class Codes: C23C 14/48 Ion implantation
• CPC Class Codes: C23C 16/507 using external electrodes, e.g. in tunnel type reactors
• CPC Class Codes: H01J 2237/2001 Maintaining constant desired temperature
• CPC Class Codes: H01J 37/321 the radio frequency energy being inductively coupled to the plasma
• CPC Class Codes: H01J 37/32174 Circuits specially adapted for controlling the RF discharge
• CPC Class Codes: H01J 37/32357 Generation remote from the workpiece, e.g. down-stream
• CPC Class Codes: H01J 37/32412 Plasma immersion ion implantation
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/318 composed of nitrides
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: Y10T 29/5313 Means to assemble electrical device

Abstract

Device-enhancing coatings are deposited on CMOS devices by successively masking with photoresist each one of the sets of N-channel and P-channel devices while unmasking or leaving unmasked the other set, and after each step of successively masking one of the sets of devices, carrying out low temperature CVD steps with a toroidal RF plasma current while applying an RF plasma bias voltage. The temperature of the workpiece is held below a threshold photoresist removal temperature. The RF bias voltage is held at a level at which the coating is deposited with a first stress when the unmasked set consists of the P-channel devices and with a second stress when the unmasked set consists of N-channel devices.

Claims

1. A method of forming coatings on a workpiece having complementary metal oxide semiconductor (CMOS) devices consisting of a set of N-channel devices and a set of P-channel devices, said method comprising:

successively masking with photoresist each one of the sets of N-channel and P-channel devices while unmasking or leaving unmasked the other set, and after each step of successively masking one of the sets of devices, carrying out the following deposition steps;

placing the workpiece in a reactor chamber facing a processing region of the chamber;

introducing a process gas containing any of a semiconductor element, nitrogen, hydrogen or oxygen into the reactor chamber;

generating a torroidal RF plasma current in a reentrant path through the processing region by applying RF plasma source power at a first frequency to a region of a reentrant conduit external of the chamber and forming a portion of the reentrant path;

applying an RF plasma bias voltage at a second frequency to the workpiece;

maintaining the temperature of the workpiece below a threshold photoresist removal temperature;

setting said RF plasma source power at a level at which the coating is deposited non-conformally; and

setting said RF bias voltage at a level at which the coating is deposited with a first stress when the unmasked set consists of the P-channel devices and with a second stress when the unmasked set consists of N-channel devices.

2. The method of claim 1 wherein said first stress is a compressive stress and said second stress is a tensile stress.

3. The method of claim 1 further comprising:

following removal of photoresist from the workpiece, coating the workpiece with a passivation layer having zero stress and high conformality by setting said RF plasma bias voltage for low or at least nearly zero stress and setting said RF plasma source power for maximum conformality while continuing to generate said RF torroidal plasma current.

4. The reactor of claim 1 wherein said first frequency is about an order of magnitude greater than said second frequency.

5. The reactor of claim 1 wherein said first frequency is an HF frequency and said second frequency is an LF frequency.

6. The reactor of claim 1 wherein said first frequency is on the order of ten or tens of MHz and said second frequency is on the order of one or a few MHz.

7. The process of claim 1 wherein said semiconductor element comprises silicon.

8. A method of forming device enhancing coatings on a workpiece having complementary metal oxide semiconductor (CMOS) devices consisting of a set of N-channel devices and a set of P-channel devices, said method comprising:

placing a first photoresist mask over one of the sets of N-channel and P-channel devices while leaving the other set exposed,

placing the workpiece in a reactor chamber facing a processing region of the chamber;

introducing a process gas containing any of a semiconductor element, nitrogen, hydrogen or oxygen into the reactor chamber;

generating a torroidal RF plasma current in a reentrant path through the processing region by applying RF plasma source power at a first frequency to a portion of an external conduit forming a portion of the reentrant path;

applying an RF plasma bias voltage at a second frequency to the workpiece;

maintaining the temperature of the workpiece under a threshold temperature below which the photoresist mask is not destroyed;

setting said RF plasma source power at a level at which the coating is deposited with a first value of conformality lying in a range between maximum conformality and maximum non-conformality;

setting said RF bias voltage at a level at which the coating is deposited with a first stress if the one set consists of the P-channel devices and with a second stress if the one set consists of N-channel devices;

removing the first photoresist mask and placing a second photoresist mask over the other of the sets of N-channel and P-channel devices,

setting said RF plasma source power at a level at which the coating is deposited with a second value of conformality lying in a the range between minimum conformality and maximum non-conformality; and

setting said RF bias voltage at a level at which the coating is deposited with a first stress if the other set consists of the P-channel devices and with a second stress if the other set consists of N-channel devices.

9. The method of claim 8 wherein said first value of conformality corresponds to a non-conformal coating, said second value of conformality corresponds to a conformal coating, said first stress is a compressive stress and said second stress is a tensile stress.

10. The method of claim 8 further comprising:

removing said second photoresist mask;

coating the workpiece with a passivation layer having zero stress and high conformality by setting said RF plasma bias voltage for zero stress and setting said RF plasma source power for maximum conformality while continuing to generate said RF torroidal plasma current.

11. The reactor of claim 8 wherein said first frequency is about an order of magnitude greater than said second frequency.

12. The reactor of claim 8 wherein said first frequency is an HF frequency and said second frequency is an LF frequency.

13. The reactor of claim 8 wherein said first frequency is on the order of ten or tens of MHz and said second frequency is on the order of one or a few MHz.

14. The process of claim 8 wherein said semiconductor element comprises silicon.

15. A method of forming a device enhancing coating on a workpiece having complementary metal oxide semiconductor (CMOS) devices consisting of a set of N-channel devices and a set of P-channel devices, said method comprising:

placing the workpiece in a reactor chamber facing a processing region of the chamber;

introducing a process gas containing any of a semiconductor element, nitrogen, hydrogen or oxygen into the reactor chamber;

generating a torroidal RF plasma current in a reentrant path through the processing region by applying RF plasma source power at a first frequency to a portion of an external conduit forming a portion of the reentrant path;

applying an RF plasma bias voltage at a second frequency to the workpiece;

maintaining the temperature of the workpiece under a threshold temperature below which the photoresist mask is not destroyed;

setting said RF bias voltage at a level lying within a range including zero volts at which the coating is deposited with one of;

(a) compressive stress, (b) tensile stress;

placing a photoresist mask over one of (a) the N-channel devices, (b) the P-channel devices, respectively,

ion implanting into the exposed portion of the coating at least one of hydrogen and helium with sufficient bias voltage and implant dose to transform the stress in said exposed portion from one of (a) compressive, (b) tensile, to the other.

16. The process of claim 15 wherein said semiconductor element comprises silicon.