Method of fabricating microconnectors

• US 7,393,774 B2
• Filed: 07/25/2006
• Issued: 07/01/2008
• Est. Priority Date: 05/03/2006
• Status: Expired due to Fees

• Current Assignee: TOUCH MICRO-SYSTEM TECHNOLOGY CORP. (Walsin Lihwa Corporation)
• Original Assignee: TOUCH MICRO-SYSTEM TECHNOLOGY CORP. (Walsin Lihwa Corporation)
• Inventors: Chiu, Ming-Yen
• Primary Examiner(s): Nguyen, Tuan H
• Application Number:
  US11/459,645
• Publication Number:
  US 20070259508A1
• Time in Patent Office: 707 Days
• Field of Search: 438/455, 438/459, 438/597, 438/618, 438/622, 438/625
• US Class Current: 438/618
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 2203/016 Temporary inorganic, non-metallic carrier, e.g. for processing or transferring
• CPC Class Codes: H05K 2203/025 Abrading, e.g. grinding or sand blasting deburring, rounding, bevelling or smoothing conductor edges H05K2203/0346
• CPC Class Codes: H05K 3/007 Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier H05K1/187, H05K3/20 and H05K3/4682 take precedence
• CPC Class Codes: H05K 3/06 the conductive material being removed chemically or electrolytically, e.g. by photo-etch process semi-additive methods H05K3/108

Abstract

A method of fabricating microconnectors. A wafer is provided, and a dielectric layer is formed on a first surface of the wafer. The dielectric layer is bonded to a support wafer, and a thinning process is performed. A second surface of the wafer is then bonded to the support wafer, and a conductive wiring pattern is formed on the dielectric layer. An insulating layer is formed on the dielectric layer and the conductive wiring pattern. A portion of the insulating layer is removed to expose the conductive wiring pattern, and a portion of the dielectric layer and the wafer is removed to divide the wafer into a plurality of microconnectors.

Claims

1. A method of fabricating microconnectors comprising:

providing a wafer comprising a first surface and a second surface;

forming a dielectric layer on the first surface of the wafer;

using a first bonding layer to combine the dielectric layer and a support wafer;

performing a thinning process to thin the wafer at the second surface of the wafer;

removing the first bonding layer, and using a second bonding layer to combine the second surface of the wafer and the support wafer;

forming a conductive wiring pattern on the dielectric layer;

forming an insulating layer on the dielectric layer and the conductive wiring pattern;

forming a mask pattern with a plurality of first openings corresponding to the conductive wiring pattern, and a plurality of second openings defining a scribe lines pattern on the insulating layer;

removing the insulating layer exposed by the first openings in order to expose the conductive wiring pattern, and removing the insulating layer, the dielectric layer and the wafer exposed by the second openings to divide the wafer into a plurality of microconnectors;

removing the mask pattern; and

removing the second bonding layer.

2. The method of claim 1, wherein the dielectric layer is an oxide layer.

3. The method of claim 1, wherein the first bonding layer comprises a thermal release tape or an ultraviolet (UV) tape.

4. The method of claim 1, wherein the support wafer comprises a silicon wafer, a glass wafer, a quartz wafer or a plastic wafer.

5. The method of claim 1, further comprising performing a preliminary thinning process to thin the second surface of the wafer before using the first bonding layer to combine the dielectric layer and the support wafer.

6. The method of claim 5, wherein the preliminary thinning process comprises a grinding process.

7. The method of claim 1, wherein the thinning process comprises a plasma etching process.

8. The method of claim 1, wherein the thinning process comprises a chemical etching process.

9. The method of claim 1, wherein the thinning process comprises a buffing polishing process.

10. The method of claim 1, wherein the second bonding layer comprises a thermal release tape or an ultraviolet (UV) tape.

11. The method of claim 1, wherein removing the wafer exposed by the second openings is accomplished by performing deep etching techniques.