Process for producing layer structures for signal distribution

• US 7,393,782 B2
• Filed: 02/04/2005
• Issued: 07/01/2008
• Est. Priority Date: 02/04/2004
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Trovarelli, Octavio, Leiberg, Wolfgang, Brintzinger, Axel
• Primary Examiner(s): EVERHART, CARIDAD
• Application Number:
  US11/051,548
• Publication Number:
  US 20050191837A1
• Time in Patent Office: 1,243 Days
• Field of Search: 438/677, 438/678, 438/725, 438/675, 257/E21.171, 257/E21.175, 257/E21.479, 257/E21.492, 257/E23.161, 257/744
• US Class Current: 438/677
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

Abstract

Structures for signal distribution are produced by applying a metallic seed layer over a semiconductor body. An insulating layer is applied over the metallic seed layer and openings in the insulating layer are produced by photolithographic patterning of the insulating layer. Each opening in the insulating layer is trapezoidal in cross section such that an upper portion of the insulating layer is wider than a lower portion of the insulating layer. A conductor is selectively formed over exposed portions of the metallic seed layer. After selectively forming the conductor, the insulating layer is anisotropically etched such that portions of the insulating layer abutting sidewalls of the conductor remain. Alternatively, a second insulating layer can be formed and anisotropically etched.

Claims

1. A process for producing layer structures for signal distribution, the process comprising:

applying a metallic seed layer over a semiconductor body;

applying a first photoresist layer over the metallic seed layer;

producing openings, which are trapezoidal in cross section, in the first photoresist layer by photolithographic patterning of the first photoresist layer;

electrolytically producing layer structures for signal distribution in the openings in the first photoresist layer;

removing the first photoresist layer;

after the first photoresist layer has been removed, applying a second photoresist layer of positive photoresist;

exposing the second photoresist layer; and

removing exposed portions of the second photoresist layer.

2. The process as claimed in claim 1, wherein portions of the metallic seed layer are removed by an etching process prior to applying the second photoresist layer.

3. The process as claimed in claim 1, wherein applying the first photoresist layer comprises applying a negative photoresist.

4. The process as claimed in claim 1, wherein applying the first photoresist layer comprises applying a positive photoresist.

5. The process as claimed in claim 1, wherein remaining portions of the second photoresist layer, after the exposure and removal, are cured in a subsequent annealing process.

6. A process for producing layer structures for signal distribution, the process comprising:

applying a metallic seed layer over a semiconductor body;

applying an insulating layer over the metallic seed layer;

producing openings in the insulating layer by photolithographic patterning of the insulating layer, each opening in the insulating layer being trapezoidal in cross section such that an upper portion of the opening is wider than a lower portion of the opening;

selectively forming a conductor over exposed portions of the metallic seed layer, the conductor producing layer structures for signal distribution in the openings in the insulating layer;

after selectively forming the conductor, anisotropically etching the insulating layer such that portions of the insulating layer abutting sidewalls of the conductor remain.

7. The process as claimed in claim 6, wherein applying an insulating layer comprises applying a positive photoresist.

8. The process as claimed in claim 7, wherein anisotropically etching the insulating layer comprises:

exposing the positive photoresist after selectively forming the conductor, the exposing step not exposing remaining portions of the positive photoresist, the remaining portions underlying the conductor; and

removing exposed portions of the positive photoresist.

9. The process as claimed in claim 8, wherein, after removing the exposed portions of the positive photoresist, the remaining parts of the photoresist layer are cured in an annealing process step.

10. The process as claimed in claim 8 and further comprising removing portions of the metallic seed layer after the exposed portions of the positive photoresist are removed.

11. The process as claimed in claim 10 wherein the metallic seed layer comprises a copper seed layer and wherein the conductor comprises copper.

12. The process as claimed in claim 11 where forming a conductor further comprises applying nickel and gold over the copper.

13. A process for producing layer structures for signal distribution, the process comprising:

forming a conductive layer over a semiconductor body;

applying a first insulating layer over the conductive layer;

producing openings in the first insulating layer by photolithographically patterning the first insulating layer, each opening in the insulating layer being trapezoidal in cross section such that an upper portion of the insulating layer is wider than a lower portion of the insulating layer;

forming a conductor within the openings and electrically contacting the conductive layer, the conductor being trapezoidal in cross section such that an upper portion of the conductor is wider than a lower portion of the conductor and such that the conductor includes sloping sidewalls;

removing the first insulating layer;

after removing the first insulating layer, forming a second insulating layer over the semiconductor body including along the sloping sidewalls of the conductor; and

anisotropically etching the second insulating layer such that portions of the insulating layer abutting the sloping sidewalls of the conductor remain.

14. The process as claimed in claim 13, and further comprising removing portions of the metallic seed layer by an etching process prior to forming the second insulating layer.

15. The process as claimed in claim 13, wherein:

forming a conductive layer over a semiconductor body comprises applying a metallic seed layer; and

wherein forming a conductor comprises electrolytically producing layer structures for signal distribution in the openings in the insulating layer.

16. The process as claimed in claim 15, wherein the metallic seed layer comprises a copper seed layer and wherein the conductor comprises copper.

17. The process as claimed in claim 16, wherein forming a conductor further comprises applying nickel and gold over the copper.

18. The process as claimed in claim 13, wherein the second insulating layer comprises a positive photoresist, wherein anisotropically etching the second insulating layer comprises:

exposing the positive photoresist after forming the conductor, the exposing step not exposing portions of the positive photoresist underlying the conductor; and

removing exposed portions of the positive photoresist.

19. The process as claimed in claim 18, wherein the first insulating layer comprises a photoresist layer.

20. The process as claimed in claim 18, and further comprising curing portions of the positive photoresist that are not removed during the step of removing exposed portions of the positive photoresist, curing being performed in an annealing process step performed after the second removing step.

21. A process for producing layer structures for signal distribution, the process comprising:

applying a metallic seed layer over a semiconductor body;

applying an insulating layer over the metallic seed layer, wherein applying the insulating layer comprises applying a positive photoresist;

producing openings in the insulating layer by photolithographic patterning of the insulating layer, each opening in the insulating layer being trapezoidal in cross section such that an upper portion of the insulating layer is wider than a lower portion of the insulating layer;

selectively forming a conductor over exposed portions of the metallic seed layer, the conductor producing layer structures for signal distribution in the openings in the insulating layer;

after selectively forming the conductor, anisotropically etching the insulating layer such that portions of the insulating layer abutting sidewalls of the conductor remain, wherein anisotropically etching the insulating layer comprises;

exposing the positive photoresist after selectively forming the conductor, the exposing step not exposing remaining portions of the positive photoresist, the remaining portions underlying the conductor; and

removing exposed portions of the positive photoresist.

22. The process as claimed in claim 21, wherein, after removing the exposed portions of the positive photoresist, the remaining parts of the positive photoresist are cured in an annealing process step.

23. The process as claimed in claim 21, further comprising removing portions of the metallic seed layer after the exposed portions of the positive photoresist are removed.

24. The process as claimed in claim 23, wherein the metallic seed layer comprises a copper seed layer and wherein the conductor comprises copper.

25. The process as claimed in claim 24, wherein forming the conductor further comprises applying nickel and gold over the copper.