Wafer level chip size packaged chip device with an N-shape junction inside and method of fabricating the same

• US 7,394,152 B2
• Filed: 11/13/2006
• Issued: 07/01/2008
• Est. Priority Date: 11/13/2006
• Status: Active Grant

• Current Assignee: China Wafer Level CSP Co., Ltd.
• Original Assignee: China Wafer Level CSP Co., Ltd.
• Inventors: Wang, Wei, Wang, Youjun, Wang, Qingwei, Xu, Qinqin, Yu, Guoqing
• Primary Examiner(s): Lee; Eugene
• Assistant Examiner(s): Gumedzoe; Peniel M
• Application Number:
  US11/559,129
• Publication Number:
  US 20080111228A1
• Time in Patent Office: 596 Days
• Field of Search: 257/690, 257/692, 257/E23.06, 257/E23.061, 257/E23.07, 257/E33.066, 257/E21.506, 438/597
• US Class Current: 257/690
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

The present invention provide a wafer level chip size packaged chip device with a N-shape junction at which external leads electrically connect to peripheral arrayed compatible pads and a method of fabricating the same. In the wafer level chip size package, with such an n-shape junction instead of a conventional T-shape junction observed in Shellcase type wafer level chip size package technology, electrical connections between compatible pads and external leads are more reliable due to larger connection area than the counterpart in the T-shape junction.

Claims

1. A wafer level chip size packaged chip device with a N-shape junction comprises:

a substrate having formed thereon a silicon chip, with a plurality of compatible pads disposed at the periphery of said chip on said substrate;

packaging structure for receiving and packaging said chip and said substrate;

a plurality of solder bumps each attached to a bottom surface of said packaging structure; and

metal leads to enable electrical connection between said compatible pads and said solder bumps;

wherein, in addition to the lateral side, a portion of both top and bottom sides of each said compatible pad is exposed so as to form a N-shape junction between said compatible pad and said lead.

2. A wafer level chip size packaged chip device with a N-shape junction as claimed in claim 1, wherein, said packaged chip device is one of a ShellOC, ShellUT or ShellOP packaged chip.

3. A method for fabricating the wafer level chip size packaged chip device with a N-shape junction as claimed in claim 1, comprising following steps:

providing a wafer, which has plurality of substrates having formed thereon a silicon chip, with plurality of compatible pads disposed at the periphery of said chip on said substrate;

disposing packaging structure for receiving and packaging said chip and said substrate;

disposing a plurality of solder bumps each attached to a bottom surface of said packaging structure; and

disposing metal leads to enable electrical connection between said compatible pads and said solder bumps;

wherein, in addition to the lateral side, a portion of both top and bottom sides of each said compatible pad is exposed so as to form a N-shape junction between said compatible pad and said lead;

cutting said wafer so as to form individual chip size packaged chip device.

4. A method for fabricating the wafer level chip size packaged chip device with a N-shape junction as claimed in claim 3, wherein,

before the step of disposing metal leads, etching the packaging structure, so as to expose the lateral side, a portion of both top and bottom sides of each said compatible pad.

5. A method for fabricating the wafer level chip size packaged chip device with a N-shape junction as claimed in claim 4, wherein said etching is performed by plasma processing.